diff --git a/src/constants.h b/src/constants.h
index 9e11faf3486024daaad708e678a72124623eef81..8a5affb1627d39ea6f4388fdddbdd749e75d9ff5 100644
--- a/src/constants.h
+++ b/src/constants.h
@@ -52,6 +52,8 @@
 #define C_N_pol 2  // Number of antenna polarizations, X and Y.
 #define C_A_pn 6  // Number of dual polarization antennas per Processing Node (PN) FPGA.
 // #define C_N_beamlets 976  // Number of beamlets per antenna band  488, 976
+#define C_V_si_db 1024  // Size of the databuffer per signal input (SI), to capture
+                        // a snapshot of the signal input data (ADC JESD204B data or WG data)
 
 #define C_200MHZ_1_CNT_NS 5  // Time of one cnt in nS
 #define C_N_CLK_PER_PPS 200000000
diff --git a/src/fpga.cpp b/src/fpga.cpp
index e89f9cc6d0743a9f0f97c2a4e0b3cf37b5ef1c04..50f763b92b5230767974b964310e991aa4cc5519 100644
--- a/src/fpga.cpp
+++ b/src/fpga.cpp
@@ -141,6 +141,8 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beamsets):
 
     pointMap->add_register("FPGA_weights_R",                                 "fpga/weights",                                nodes.size(), C_S_pn*nBeamsets*C_N_sub_bf, "RO", REG_FORMAT_INT16);
     pointMap->add_register("FPGA_weights_RW",                                "fpga/weights",                                nodes.size(), C_S_pn*nBeamsets*C_N_sub_bf, "RW", REG_FORMAT_INT16);
+    
+    pointMap->add_register("FPGA_signal_input_data_buffer_R",                "fpga/signal_input_data_buffer",               nodes.size(), C_S_pn*C_V_si_db, "RO", REG_FORMAT_INT16);
 }
 
 Fpga::~Fpga()
diff --git a/src/periph/fpga.cpp b/src/periph/fpga.cpp
index 1da1062d55f4b10c295f859655c2dd6c816588e0..9439435fe23a4c4352fde87d899ba8aedc6ad233 100644
--- a/src/periph/fpga.cpp
+++ b/src/periph/fpga.cpp
@@ -300,6 +300,9 @@ bool Periph_fpga::read(TermOutput& termout, const string addr,
         else if (addr == "fpga/subband_weights") {
             retval = read_subband_weights(termout, format);
         }
+        else if (addr == "fpga/signal_input_data_buffer") {
+            retval = read_signal_input_data_buffer(termout, format);
+        }
         else {
             throw runtime_error("address " + addr + " not found!");
         }
@@ -2375,6 +2378,24 @@ bool Periph_fpga::read_subband_weights(TermOutput& termout, int format) {
     return retval;
 }
 
+bool Periph_fpga::read_signal_input_data_buffer(TermOutput& termout, int format) {
+    bool retval = true;
+    uint32_t *_ptr = (uint32_t *)termout.val;
+
+    string regname;
+    uint32_t span;
+
+    for (uint i=0; i<C_S_pn; i++) {
+        regname = "mm/0/RAM_DIAG_DATA_BUFFER_BSN/" + to_string(i) + "/data";
+        span = mmap->getSpan((regname));
+        retval = Read(regname, _ptr);
+        _ptr += span;
+    }
+    termout.nof_vals = C_S_pn * C_V_si_db;
+    termout.datatype = format;
+    return retval;
+}
+
 bool Periph_fpga::read_time_since_last_pps(TermOutput& termout, int format, int mode) {
     bool retval = true;
     if (mode == R_UCP) {
diff --git a/src/periph/fpga.h b/src/periph/fpga.h
index 24337ee3dda554a45c910ef823c4aee356647f99..20697ab26c8a617f1b0962b95e5836598cb9feb5 100644
--- a/src/periph/fpga.h
+++ b/src/periph/fpga.h
@@ -187,6 +187,8 @@ private:
   bool write_subband_weights(const char *data);
   bool read_subband_weights(TermOutput& termout, int format);
 
+  bool read_signal_input_data_buffer(TermOutput& termout, int format);
+
   bool read_sdp_info_block_period(TermOutput& termout, int format);
 
   bool read_time_since_last_pps(TermOutput& termout, int format, int mode);