L2SDP-356, add FPGA_subband_weights_R/_RW, changed name...

L2SDP-356, add FPGA_subband_weights_R/_RW, changed name FPGA_sst_offload_selector_* to FPGA_sst_offload_weighted_subbands_* and removed unused args from Write command.

src/constants.h

@@ -29,6 +29,7 @@
 #ifndef CONSTANTS_H
 #define CONSTANTS_H
 
+#define C_N_pn 16
 #define C_S_pn 12
 #define C_W_adc 14
 #define C_F_adc 200E6
@@ -41,4 +42,7 @@
 
 #define C_BSN_LATENCY 20000  // 1 period = 5.12us, 20000 = +/- 100ms
 
+#define C_Q_fft 2
+#define C_N_sub 512
+
 #endif

src/fpga.cpp

@@ -61,8 +61,8 @@ Fpga::Fpga(list<class Node*>& nodelist)
     pointMap->add_register("FPGA_version_R",                                 "fpga/name",                                   nodes.size(), 1, "RO", REG_FORMAT_STRING);
     pointMap->add_register("FPGA_firmware_version_R",                        "fpga/firmware_version",                       nodes.size(), 1, "RO", REG_FORMAT_STRING);
     pointMap->add_register("FPGA_hardware_version_R",                        "fpga/hardware_version",                       nodes.size(), 1, "RO", REG_FORMAT_STRING);
-    pointMap->add_register("FPGA_sst_offload_selector_R",                    "fpga/sst_offload_selector",                   nodes.size(), 1, "RO", REG_FORMAT_BOOLEAN);
-    pointMap->add_register("FPGA_sst_offload_selector_RW",                   "fpga/sst_offload_selector",                   nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN);
+    pointMap->add_register("FPGA_sst_offload_weighted_subbands_R",           "fpga/sst_offload_weighted_subbands",          nodes.size(), 1, "RO", REG_FORMAT_BOOLEAN);
+    pointMap->add_register("FPGA_sst_offload_weighted_subbands_RW",          "fpga/sst_offload_weighted_subbands",          nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN);
     pointMap->add_register("FPGA_sst_offload_enable_R",                      "fpga/sst_offload_enable",                     nodes.size(), 1, "RO", REG_FORMAT_BOOLEAN);
     pointMap->add_register("FPGA_sst_offload_enable_RW",                     "fpga/sst_offload_enable",                     nodes.size(), 1, "RW", REG_FORMAT_BOOLEAN);
     pointMap->add_register("FPGA_sst_offload_hdr_eth_destination_mac_R",     "fpga/sst_offload_hdr_eth_destination_mac",    nodes.size(), 1, "RO", REG_FORMAT_STRING);
@@ -106,6 +106,9 @@ Fpga::Fpga(list<class Node*>& nodelist)
     pointMap->add_register("FPGA_signal_input_samples_delay_R",              "fpga/signal_input_samples_delay",             nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
     pointMap->add_register("FPGA_signal_input_samples_delay_RW",             "fpga/signal_input_samples_delay",             nodes.size(), C_S_pn, "RW", REG_FORMAT_UINT32);
     
+    pointMap->add_register("FPGA_subband_weights_R",                         "fpga/subband_weights",                        nodes.size(), C_S_pn*C_N_sub, "RO", REG_FORMAT_UINT32);
+    pointMap->add_register("FPGA_subband_weights_RW",                        "fpga/subband_weights",                        nodes.size(), C_S_pn*C_N_sub, "RW", REG_FORMAT_UINT32);
+
     uint32_t scrap_span = 0;
     uint32_t scrap_span_next = 0;
     uint32_t scrap_span_prev = 0;

src/periph/fpga.h

@@ -73,14 +73,14 @@ private:
            Flash_fact_sector_start, Flash_fact_sector_end, Flash_select;
 
   bool Read(const std::string addr_str, uint32_t *data_ptr, bool use_mask_shift);
-  bool Write(const std::string addr_str, const uint32_t nvalues, uint32_t *data_ptr, bool use_shift_mask);
+  bool Write(const std::string addr_str, uint32_t *data_ptr, bool use_shift_mask);
   uint32_t mask_shift(const std::string addr_str, uint32_t data);
   uint32_t shift_mask(const std::string addr_str, uint32_t data);
 
   bool flash_erase_sector(uint32_t sector);
   bool flash_erase();
   bool flash_pages(uint32_t *data, const uint len);
-  bool flash_page(uint32_t *data, const uint len);
+  bool flash_page(uint32_t *data);
   bool flash_prot(uint32_t *data);
   bool wait_while_epcs_busy(uint sleeptime);
   std::string read_design_name();
@@ -98,46 +98,46 @@ private:
   bool read_fpga_temperature(TermOutput& termout, int format);
 
   bool read_fpga_scrap(TermOutput& termout, int format);
-  bool write_fpga_scrap(uint32_t *data, uint len);
+  bool write_fpga_scrap(uint32_t *data);
 
   bool read_fpga_weights(TermOutput& termout, int format);
-  bool write_fpga_weights(const uint32_t *data, uint nvalues);
+  bool write_fpga_weights(const uint32_t *data);
 
-  bool read_sst_offload_selector(TermOutput& termout, int format);
-  bool write_sst_offload_selector(uint32_t *data, uint32_t nvalues);
+  bool read_sst_offload_weighted_subbands(TermOutput& termout, int format);
+  bool write_sst_offload_weighted_subbands(uint32_t *data);
 
   bool read_sst_offload_enable(TermOutput& termout, int format);
-  bool write_sst_offload_enable(uint32_t *data, uint32_t nvalues);
+  bool write_sst_offload_enable(uint32_t *data);
 
   bool read_sst_offload_hdr_eth_destination_mac(TermOutput& termout, int format);
-  bool write_sst_offload_hdr_eth_destination_mac(const char *data, uint32_t nvalues);
+  bool write_sst_offload_hdr_eth_destination_mac(const char *data);
 
   bool read_sst_offload_hdr_ip_destination_address(TermOutput& termout, int format);
-  bool write_sst_offload_hdr_ip_destination_address(const char *data, uint32_t nvalues);
+  bool write_sst_offload_hdr_ip_destination_address(const char *data);
 
   bool read_sst_offload_hdr_udp_destination_port(TermOutput& termout, int format);
-  bool write_sst_offload_hdr_udp_destination_port(uint32_t *data, uint32_t nvalues);
+  bool write_sst_offload_hdr_udp_destination_port(uint32_t *data);
 
   bool read_processing_enable(TermOutput& termout, int format);
-  bool write_processing_enable(uint32_t *data, uint32_t nvalues);
+  bool write_processing_enable(uint32_t *data);
 
   bool read_sdp_info_station_id(TermOutput& termout, int format);
-  bool write_sdp_info_station_id(uint32_t *data, uint32_t nvalues);
+  bool write_sdp_info_station_id(uint32_t *data);
   bool read_sdp_info_observation_id(TermOutput& termout, int format);
-  bool write_sdp_info_observation_id(uint32_t *data, uint32_t nvalues);
+  bool write_sdp_info_observation_id(uint32_t *data);
   bool read_sdp_info_nyquist_sampling_zone_index(TermOutput& termout, int format);
-  bool write_sdp_info_nyquist_sampling_zone_index(uint32_t *data, uint32_t nvalues);
+  bool write_sdp_info_nyquist_sampling_zone_index(uint32_t *data);
   bool read_sdp_info_antenna_band_index(TermOutput& termout, int format);
   bool read_sdp_info_f_adc(TermOutput& termout, int format);
   bool read_sdp_info_fsub_type(TermOutput& termout, int format);
   bool read_wg_enable(TermOutput& termout, int format);
 
-  bool write_wg_enable(uint32_t *data, uint32_t nvalues);
+  bool write_wg_enable(uint32_t *data);
   bool read_wg_amplitude(TermOutput& termout, int format);
-  bool write_wg_amplitude(uint32_t *data, uint32_t nvalues);
+  bool write_wg_amplitude(uint32_t *data);
   bool read_wg_phase(TermOutput& termout, int format);
-  bool write_wg_phase (uint32_t *data, uint32_t nvalues);
-  bool write_wg_frequency(uint32_t *data, uint32_t nvalues);
+  bool write_wg_phase (uint32_t *data);
+  bool write_wg_frequency(uint32_t *data);
   bool read_wg_frequency(TermOutput& termout, int format);
 
   bool read_bsn_monitor_input_sync_timeout(TermOutput& termout, int format, int mode);
@@ -151,9 +151,11 @@ private:
   bool read_jesd204b_csr_rx_err0(TermOutput& termout, int format, int mode);
   bool read_jesd204b_csr_rx_err1(TermOutput& termout, int format, int mode);
   
-  bool write_signal_input_samples_delay(uint32_t *data, uint32_t nvalues);
+  bool write_signal_input_samples_delay(uint32_t *data);
   bool read_signal_input_samples_delay(TermOutput& termout, int format);
 
+  bool write_subband_weights(uint32_t *data);
+  bool read_subband_weights(TermOutput& termout, int format);
 
   bool read_sdp_info_block_period(TermOutput& termout, int format);