diff --git a/src/fpga.cpp b/src/fpga.cpp
index ddcccf83d6670245dc07f9b4a704e6a0630b3ceb..5c01a0bddbfee6af06d68cf30cee1f5995dc8d6c 100644
--- a/src/fpga.cpp
+++ b/src/fpga.cpp
@@ -127,10 +127,9 @@ FpgaMap::FpgaMap(list<class Node*>& nodelist, const int32_t n_beamsets):
pointMap->add_register("FPGA_wg_phase_RW", "fpga/wg_phase", nodes.size(), C_S_pn, "RW", REG_FORMAT_DOUBLE);
pointMap->add_register("FPGA_wg_frequency_R", "fpga/wg_frequency", nodes.size(), C_S_pn, "RO", REG_FORMAT_DOUBLE);
pointMap->add_register("FPGA_wg_frequency_RW", "fpga/wg_frequency", nodes.size(), C_S_pn, "RW", REG_FORMAT_DOUBLE);
- pointMap->add_register("FPGA_bsn_monitor_input_bsn_R", "fpga/bsn_monitor_input_bsn", nodes.size(), 1, "RO", REG_FORMAT_INT64);
- pointMap->add_register("FPGA_bsn_monitor_input_nof_packets_R", "fpga/bsn_monitor_input_nof_packets", nodes.size(), 1, "RO", REG_FORMAT_INT32);
- pointMap->add_register("FPGA_bsn_monitor_input_nof_valid_R", "fpga/bsn_monitor_input_nof_valid", nodes.size(), 1, "RO", REG_FORMAT_INT32);
- pointMap->add_register("FPGA_bsn_monitor_input_nof_err_R", "fpga/bsn_monitor_input_nof_err", nodes.size(), 1, "RO", REG_FORMAT_INT32);
+ pointMap->add_register("FPGA_signal_input_bsn_R", "fpga/signal_input_bsn", nodes.size(), 1, "RO", REG_FORMAT_INT64);
+ pointMap->add_register("FPGA_signal_input_nof_packets_R", "fpga/signal_input_nof_packets", nodes.size(), 1, "RO", REG_FORMAT_INT32);
+ pointMap->add_register("FPGA_signal_input_nof_samples_R", "fpga/signal_input_nof_samples", nodes.size(), 1, "RO", REG_FORMAT_INT32);
pointMap->add_register("FPGA_jesd204b_csr_rbd_count_R", "fpga/jesd204b_csr_rbd_count", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_jesd204b_csr_dev_syncn_R", "fpga/jesd204b_csr_dev_syncn", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_jesd204b_rx_err0_R", "fpga/jesd204b_rx_err0", nodes.size(), C_S_pn, "RO", REG_FORMAT_UINT32);
diff --git a/src/periph/fpga.cpp b/src/periph/fpga.cpp
index b87dc146e62b24c24de0db4e02c6310ecd051039..86532cfefae814283195835f2c478310172a1037 100644
--- a/src/periph/fpga.cpp
+++ b/src/periph/fpga.cpp
@@ -70,13 +70,12 @@ Periph_fpga::Periph_fpga(uint global_nr, string ipaddr, uint n_beamsets):
current_design_name("-"),
current_hw_version(0),
current_fw_version("-.-"),
- bsn_input_sync_timeout(false),
- bsn_input_bsn(0),
+ signal_input_sync_timeout(false),
+ signal_input_bsn(0),
xst_input_bsn_at_sync(0),
xst_output_sync_bsn(0),
- bsn_input_nof_packets(0),
- bsn_input_nof_valid(0),
- bsn_input_nof_err(0),
+ signal_input_nof_packets(0),
+ signal_input_nof_samples(0),
sst_offload_nof_packets(0),
sst_offload_nof_valid(0),
bst_offload_nof_packets {0},
@@ -134,24 +133,23 @@ Periph_fpga::~Periph_fpga()
*/
bool Periph_fpga::clear_fw_values()
{
- current_design_name = "-";
- current_hw_version = 0;
- current_fw_version = "-.-";
- bsn_input_sync_timeout = false;
- bsn_input_bsn = 0;
- xst_input_bsn_at_sync = 0;
- xst_output_sync_bsn = 0;
- bsn_input_nof_packets = 0;
- bsn_input_nof_valid = 0;
- bsn_input_nof_err = 0;
- sst_offload_nof_packets = 0;
- sst_offload_nof_valid = 0;
- xst_offload_nof_packets = 0;
- xst_offload_nof_valid = 0;
- pps_offset_cnt = 0;
- pps_expected_cnt = 0;
- pps_present = false;
- pps_capture_cnt = 0;
+ current_design_name = "-";
+ current_hw_version = 0;
+ current_fw_version = "-.-";
+ signal_input_sync_timeout = false;
+ signal_input_bsn = 0;
+ xst_input_bsn_at_sync = 0;
+ xst_output_sync_bsn = 0;
+ signal_input_nof_packets = 0;
+ signal_input_nof_samples = 0;
+ sst_offload_nof_packets = 0;
+ sst_offload_nof_valid = 0;
+ xst_offload_nof_packets = 0;
+ xst_offload_nof_valid = 0;
+ pps_offset_cnt = 0;
+ pps_expected_cnt = 0;
+ pps_present = false;
+ pps_capture_cnt = 0;
for (uint i=0; i<C_N_beamsets_sdp; i++) {
bst_offload_nof_packets[i] = 0;
@@ -198,12 +196,11 @@ bool Periph_fpga::read(char *data, const string addr, const string type, const i
else { // "fpga/..."
if (addr == "fpga/time_since_last_pps") { retval = read_time_since_last_pps(data, format, R_MEM); }
else if (addr == "fpga/pps_capture_cnt") { retval = read_pps_capture_cnt(data, format, R_MEM); }
- else if (addr == "fpga/bsn_monitor_input_bsn") { retval = read_bsn_monitor_input_bsn(data, format, R_MEM); }
+ else if (addr == "fpga/signal_input_bsn") { retval = read_signal_input_bsn(data, format, R_MEM); }
else if (addr == "fpga/xst_input_sync_at_bsn") { retval = read_xst_input_sync_at_bsn(data, format, R_MEM); }
else if (addr == "fpga/xst_output_sync_bsn") { retval = read_xst_output_sync_bsn(data, format, R_MEM); }
- else if (addr == "fpga/bsn_monitor_input_nof_packets") { retval = read_bsn_monitor_input_nof_packets(data, format, R_MEM); }
- else if (addr == "fpga/bsn_monitor_input_nof_valid") { retval = read_bsn_monitor_input_nof_valid(data, format, R_MEM); }
- else if (addr == "fpga/bsn_monitor_input_nof_err") { retval = read_bsn_monitor_input_nof_err(data, format, R_MEM); }
+ else if (addr == "fpga/signal_input_nof_packets") { retval = read_signal_input_nof_packets(data, format, R_MEM); }
+ else if (addr == "fpga/signal_input_nof_samples") { retval = read_signal_input_nof_samples(data, format, R_MEM); }
else if (addr == "fpga/jesd204b_csr_dev_syncn") { retval = read_jesd204b_csr_dev_syncn(data, format, R_MEM); }
else if (addr == "fpga/jesd204b_csr_rbd_count") { retval = read_jesd204b_csr_rbd_count(data, format, R_MEM); }
else if (addr == "fpga/jesd204b_rx_err0") { retval = read_jesd204b_rx_err0(data, format, R_MEM); }
@@ -401,13 +398,12 @@ bool Periph_fpga::monitor(char *data)
}
read_time_since_last_pps(data, REG_FORMAT_INT64, R_UCP);
read_pps_capture_cnt(data, REG_FORMAT_UINT32, R_UCP);
- read_bsn_monitor_input_sync_timeout(data, REG_FORMAT_INT64, R_UCP);
- read_bsn_monitor_input_bsn(data, REG_FORMAT_INT64, R_UCP);
+ read_signal_input_sync_timeout(data, REG_FORMAT_INT64, R_UCP);
+ read_signal_input_bsn(data, REG_FORMAT_INT64, R_UCP);
read_xst_input_sync_at_bsn(data, REG_FORMAT_INT64, R_UCP);
read_xst_output_sync_bsn(data, REG_FORMAT_INT64, R_UCP);
- read_bsn_monitor_input_nof_packets(data, REG_FORMAT_INT32, R_UCP);
- read_bsn_monitor_input_nof_valid(data, REG_FORMAT_INT32, R_UCP);
- read_bsn_monitor_input_nof_err(data, REG_FORMAT_INT32, R_UCP);
+ read_signal_input_nof_packets(data, REG_FORMAT_INT32, R_UCP);
+ read_signal_input_nof_samples(data, REG_FORMAT_INT32, R_UCP);
read_jesd204b_csr_rbd_count(data, REG_FORMAT_UINT32, R_UCP);
read_jesd204b_csr_dev_syncn(data, REG_FORMAT_UINT32, R_UCP);
read_jesd204b_rx_err0(data, REG_FORMAT_UINT32, R_UCP);
@@ -1939,22 +1935,22 @@ bool Periph_fpga::write_wg_frequency(const char *data) {
return retval;
}
-bool Periph_fpga::read_bsn_monitor_input_sync_timeout(char *data, int format, int mode) {
+bool Periph_fpga::read_signal_input_sync_timeout(char *data, int format, int mode) {
bool retval = true;
uint32_t sdp_data;
string regname;
regname = "mm/0/REG_BSN_MONITOR_INPUT/0/sync_timeout";
retval = Read(regname, &sdp_data);
- bsn_input_sync_timeout = (bool)sdp_data;
+ signal_input_sync_timeout = (bool)sdp_data;
return retval;
}
-bool Periph_fpga::read_bsn_monitor_input_bsn(char *data, int format, int mode) {
+bool Periph_fpga::read_signal_input_bsn(char *data, int format, int mode) {
bool retval = true;
- int64_t bsn = bsn_input_bsn;
+ int64_t bsn = signal_input_bsn;
if (mode == R_UCP) {
- if (bsn_input_sync_timeout == true) {
+ if (signal_input_sync_timeout == true) {
bsn = -1;
} else {
uint32_t sdp_data[2];
@@ -1967,15 +1963,15 @@ bool Periph_fpga::read_bsn_monitor_input_bsn(char *data, int format, int mode) {
}
int64_t *_ptr = (int64_t *)data;
*_ptr = bsn;
- bsn_input_bsn = bsn;
+ signal_input_bsn = bsn;
return retval;
}
-bool Periph_fpga::read_bsn_monitor_input_nof_packets(char *data, int format, int mode) {
+bool Periph_fpga::read_signal_input_nof_packets(char *data, int format, int mode) {
bool retval = true;
- int32_t nof_packets = bsn_input_nof_packets;
+ int32_t nof_packets = signal_input_nof_packets;
if (mode == R_UCP) {
- if (bsn_input_sync_timeout == true) {
+ if (signal_input_sync_timeout == true) {
nof_packets = -1;
} else {
uint32_t sdp_data;
@@ -1987,15 +1983,15 @@ bool Periph_fpga::read_bsn_monitor_input_nof_packets(char *data, int format, int
}
int32_t *_ptr = (int32_t *)data;
*_ptr = nof_packets;
- bsn_input_nof_packets = nof_packets;
+ signal_input_nof_packets = nof_packets;
return retval;
}
-bool Periph_fpga::read_bsn_monitor_input_nof_valid(char *data, int format, int mode) {
+bool Periph_fpga::read_signal_input_nof_samples(char *data, int format, int mode) {
bool retval = true;
- int32_t nof_valid = bsn_input_nof_valid;
+ int32_t nof_valid = signal_input_nof_samples;
if (mode == R_UCP) {
- if (bsn_input_sync_timeout == true) {
+ if (signal_input_sync_timeout == true) {
nof_valid = -1;
} else {
uint32_t sdp_data;
@@ -2007,27 +2003,7 @@ bool Periph_fpga::read_bsn_monitor_input_nof_valid(char *data, int format, int m
}
int32_t *_ptr = (int32_t *)data;
*_ptr = nof_valid;
- bsn_input_nof_valid = nof_valid;
- return retval;
-}
-
-bool Periph_fpga::read_bsn_monitor_input_nof_err(char *data, int format, int mode) {
- bool retval = true;
- int32_t nof_err = bsn_input_nof_err;
- if (mode == R_UCP) {
- if (bsn_input_sync_timeout == true) {
- nof_err = -1;
- } else {
- uint32_t sdp_data;
- string regname;
- regname = "mm/0/REG_BSN_MONITOR_INPUT/0/nof_err";
- retval = Read(regname, &sdp_data);
- nof_err = (int32_t)sdp_data;
- }
- }
- int32_t *_ptr = (int32_t *)data;
- *_ptr = nof_err;
- bsn_input_nof_err = nof_err;
+ signal_input_nof_samples = nof_valid;
return retval;
}
diff --git a/src/periph/fpga.h b/src/periph/fpga.h
index 3a540f78754b957f04c2762961ff55c30c1907ed..91af78ba1b4aef36d1bbebf8f3ff01fafc919b6b 100644
--- a/src/periph/fpga.h
+++ b/src/periph/fpga.h
@@ -60,13 +60,12 @@ private:
uint current_hw_version;
std::string current_fw_version;
- bool bsn_input_sync_timeout;
- int64_t bsn_input_bsn;
+ bool signal_input_sync_timeout;
+ int64_t signal_input_bsn;
int64_t xst_input_bsn_at_sync;
int64_t xst_output_sync_bsn;
- int32_t bsn_input_nof_packets;
- int32_t bsn_input_nof_valid;
- int32_t bsn_input_nof_err;
+ int32_t signal_input_nof_packets;
+ int32_t signal_input_nof_samples;
int32_t sst_offload_nof_packets;
int32_t sst_offload_nof_valid;
int32_t bst_offload_nof_packets[C_N_beamsets_sdp];
@@ -190,11 +189,10 @@ private:
bool write_wg_frequency(const char *data);
bool read_wg_frequency(char *data, int format);
- bool read_bsn_monitor_input_sync_timeout(char *data, int format, int mode);
- bool read_bsn_monitor_input_bsn(char *data, int format, int mode);
- bool read_bsn_monitor_input_nof_packets(char *data, int format, int mode);
- bool read_bsn_monitor_input_nof_valid(char *data, int format, int mode);
- bool read_bsn_monitor_input_nof_err(char *data, int format, int mode);
+ bool read_signal_input_sync_timeout(char *data, int format, int mode);
+ bool read_signal_input_bsn(char *data, int format, int mode);
+ bool read_signal_input_nof_packets(char *data, int format, int mode);
+ bool read_signal_input_nof_samples(char *data, int format, int mode);
bool read_jesd204b_csr_rbd_count(char *data, int format, int mode);
bool read_jesd204b_csr_dev_syncn(char *data, int format, int mode);