From 75ebf51ca5ebfeb4bd46381dcfac35bcafc118b2 Mon Sep 17 00:00:00 2001
From: Gijs <schoonderbeek@astron.nl>
Date: Mon, 25 Oct 2021 09:39:07 +0000
Subject: [PATCH] Added direct OPC-UA example on the bottom
---
Jupyter_Pages/UNB2C_HW_Monitor.ipynb | 295 +++++++++++++++------------
1 file changed, 160 insertions(+), 135 deletions(-)
diff --git a/Jupyter_Pages/UNB2C_HW_Monitor.ipynb b/Jupyter_Pages/UNB2C_HW_Monitor.ipynb
index d2607f6..c73fa13 100644
--- a/Jupyter_Pages/UNB2C_HW_Monitor.ipynb
+++ b/Jupyter_Pages/UNB2C_HW_Monitor.ipynb
@@ -5,13 +5,15 @@
"id": "e73610a1",
"metadata": {},
"source": [
- "Jupyter page started by Gijs, copy past from others, with a little bit of my self ;-)\n",
+ "# Script to read out UniBoard2 HW information\n",
+ "\n",
+ "Jupyter page started by Gijs, copy past from others, with a little bit of my self ;-) <br>\n",
"Can be used to readout the hardware monitoring points on the UniBoard2c"
]
},
{
"cell_type": "code",
- "execution_count": 1,
+ "execution_count": 76,
"id": "c2ace952",
"metadata": {},
"outputs": [],
@@ -22,7 +24,7 @@
},
{
"cell_type": "code",
- "execution_count": 2,
+ "execution_count": 77,
"id": "dd54c19e",
"metadata": {
"scrolled": true
@@ -32,68 +34,7 @@
"name": "stdout",
"output_type": "stream",
"text": [
- "Device is now in on state\n",
- "Atttibutes of pcc are: \n",
- "*********\n",
- "version_R\n",
- "opcua_missing_attributes_R\n",
- "UNB2TR_translator_busy_R\n",
- "UNB2_DC_DC_48V_12V_IOUT_R\n",
- "UNB2_DC_DC_48V_12V_TEMP_R\n",
- "UNB2_DC_DC_48V_12V_VIN_R\n",
- "UNB2_DC_DC_48V_12V_VOUT_R\n",
- "UNB2_EEPROM_Serial_Number_R\n",
- "UNB2_EEPROM_Unique_ID_R\n",
- "UNB2_FPGA_DDR4_SLOT_TEMP_R\n",
- "UNB2_FPGA_POL_CORE_IOUT_R\n",
- "UNB2_FPGA_POL_CORE_TEMP_R\n",
- "UNB2_FPGA_POL_CORE_VOUT_R\n",
- "UNB2_FPGA_POL_ERAM_IOUT_R\n",
- "UNB2_FPGA_POL_ERAM_TEMP_R\n",
- "UNB2_FPGA_POL_ERAM_VOUT_R\n",
- "UNB2_FPGA_POL_HGXB_IOUT_R\n",
- "UNB2_FPGA_POL_HGXB_TEMP_R\n",
- "UNB2_FPGA_POL_HGXB_VOUT_R\n",
- "UNB2_FPGA_POL_PGM_IOUT_R\n",
- "UNB2_FPGA_POL_PGM_TEMP_R\n",
- "UNB2_FPGA_POL_PGM_VOUT_R\n",
- "UNB2_FPGA_POL_RXGXB_IOUT_R\n",
- "UNB2_FPGA_POL_RXGXB_TEMP_R\n",
- "UNB2_FPGA_POL_RXGXB_VOUT_R\n",
- "UNB2_FPGA_POL_TXGXB_IOUT_R\n",
- "UNB2_FPGA_POL_TXGXB_TEMP_R\n",
- "UNB2_FPGA_POL_TXGXB_VOUT_R\n",
- "UNB2_FPGA_QSFP_CAGE_LOS_R\n",
- "UNB2_FPGA_QSFP_CAGE_TEMP_R\n",
- "UNB2_Front_Panel_LED_R\n",
- "UNB2_Front_Panel_LED_RW\n",
- "UNB2_I2C_bus_DDR4_error_R\n",
- "UNB2_I2C_bus_error_R\n",
- "UNB2_I2C_bus_FPGA_PS_error_R\n",
- "UNB2_I2C_bus_PS_error_R\n",
- "UNB2_I2C_bus_QSFP_error_R\n",
- "UNB2_mask_RW\n",
- "UNB2_POL_CLOCK_IOUT_R\n",
- "UNB2_POL_CLOCK_TEMP_R\n",
- "UNB2_POL_CLOCK_VOUT_R\n",
- "UNB2_POL_QSFP_N01_IOUT_R\n",
- "UNB2_POL_QSFP_N01_TEMP_R\n",
- "UNB2_POL_QSFP_N01_VOUT_R\n",
- "UNB2_POL_QSFP_N23_IOUT_R\n",
- "UNB2_POL_QSFP_N23_TEMP_R\n",
- "UNB2_POL_QSFP_N23_VOUT_R\n",
- "UNB2_POL_SWITCH_1V2_IOUT_R\n",
- "UNB2_POL_SWITCH_1V2_TEMP_R\n",
- "UNB2_POL_SWITCH_1V2_VOUT_R\n",
- "UNB2_POL_SWITCH_PHY_IOUT_R\n",
- "UNB2_POL_SWITCH_PHY_TEMP_R\n",
- "UNB2_POL_SWITCH_PHY_VOUT_R\n",
- "UNB2_PWR_off_R\n",
- "UNB2_PWR_off_RW\n",
- "State\n",
- "Status\n",
- "*********\n",
- "\n"
+ "UNB2-HW is now in on state\n"
]
}
],
@@ -112,23 +53,25 @@
" unb2c.on()\n",
"state = str(unb2c.state())\n",
"if state == \"ON\":\n",
- " print(\"Device is now in on state\")\n",
+ " print(\"UNB2-HW is now in on state\")\n",
"else:\n",
- " print(\"warning, expected device to be in on state, is: \", state)\n",
- "#\n",
- "# Print the available attributes\n",
- "#\n",
- "print(\"Atttibutes of pcc are: \\n*********\")\n",
- "attr_names = unb2c.get_attribute_list()\n",
- "for i in attr_names:\n",
- " print(i)\n",
- "# exec(\"value = print(i, d.{})\".format(i))\n",
- "print(\"*********\\n\") \n"
+ " print(\"warning, expected UNB2-HW to be in on state, is: \", state)\n",
+ "\n",
+ "if 0:\n",
+ " #\n",
+ " # Print the available attributes\n",
+ " #\n",
+ " print(\"Atttibutes of unb2 are: \\n*********\")\n",
+ " attr_names = unb2c.get_attribute_list()\n",
+ " for i in attr_names:\n",
+ " print(i)\n",
+ " # exec(\"value = print(i, d.{})\".format(i))\n",
+ " print(\"*********\\n\") \n"
]
},
{
"cell_type": "code",
- "execution_count": 10,
+ "execution_count": 79,
"id": "51d0443c",
"metadata": {
"scrolled": true
@@ -142,14 +85,14 @@
"|---------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | Node nr. | Core pol | ERAM pol | TrRx pol | TxHx pol | IO pol |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 0 | 30.2 °C | 36.2 °C | 32.6 °C | 36.9 °C | 38.8 °C |\n",
- "| 0 | 1 | 31.5 °C | 37.4 °C | 35.4 °C | 40.3 °C | 41.4 °C |\n",
- "| 0 | 2 | 30.2 °C | 38.4 °C | 33.6 °C | 40.8 °C | 42.1 °C |\n",
- "| 0 | 3 | 31.5 °C | 39.0 °C | 34.6 °C | 38.6 °C | 38.1 °C |\n",
- "| 1 | 0 | 30.2 °C | 36.2 °C | 32.6 °C | 36.9 °C | 38.8 °C |\n",
- "| 1 | 1 | 31.5 °C | 37.4 °C | 35.4 °C | 40.3 °C | 41.4 °C |\n",
- "| 1 | 2 | 30.2 °C | 38.4 °C | 33.6 °C | 40.8 °C | 42.1 °C |\n",
- "| 1 | 3 | 31.5 °C | 39.0 °C | 34.6 °C | 38.2 °C | 38.1 °C |\n",
+ "| 0 | 0 | 29.84 °C | 36.25 °C | 32.75 °C | 37.00 °C | 39.00 °C |\n",
+ "| 0 | 1 | 31.50 °C | 37.56 °C | 35.69 °C | 40.75 °C | 41.38 °C |\n",
+ "| 0 | 2 | 32.06 °C | 38.88 °C | 34.06 °C | 40.62 °C | 42.19 °C |\n",
+ "| 0 | 3 | 32.31 °C | 39.31 °C | 35.00 °C | 38.50 °C | 38.31 °C |\n",
+ "| 1 | 0 | nan °C | nan °C | nan °C | nan °C | nan °C |\n",
+ "| 1 | 1 | nan °C | nan °C | nan °C | nan °C | nan °C |\n",
+ "| 1 | 2 | nan °C | nan °C | nan °C | nan °C | nan °C |\n",
+ "| 1 | 3 | nan °C | nan °C | nan °C | nan °C | nan °C |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"FPGA point-of-load converte voltages\n",
@@ -160,38 +103,38 @@
"| 0 | 1 | 0.95 V | 0.90 V | 0.90 V | 0.90 V | 1.80 V | 1.80 V |\n",
"| 0 | 2 | 0.95 V | 0.90 V | 0.90 V | 0.90 V | 1.80 V | 1.80 V |\n",
"| 0 | 3 | 0.95 V | 0.90 V | 0.90 V | 0.90 V | 1.80 V | 1.80 V |\n",
- "| 1 | 0 | 0.95 V | 0.90 V | 0.90 V | 0.90 V | 1.80 V | 1.80 V |\n",
- "| 1 | 1 | 0.95 V | 0.90 V | 0.90 V | 0.90 V | 1.80 V | 1.80 V |\n",
- "| 1 | 2 | 0.95 V | 0.90 V | 0.90 V | 0.90 V | 1.80 V | 1.80 V |\n",
- "| 1 | 3 | 0.95 V | 0.90 V | 0.90 V | 0.90 V | 1.80 V | 1.80 V |\n",
+ "| 1 | 0 | 0.95 V | nan V | nan V | nan V | nan V | nan V |\n",
+ "| 1 | 1 | 0.95 V | nan V | nan V | nan V | nan V | nan V |\n",
+ "| 1 | 2 | 0.95 V | nan V | nan V | nan V | nan V | nan V |\n",
+ "| 1 | 3 | 0.95 V | nan V | nan V | nan V | nan V | nan V |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"FPGA point-of-load converter output currents\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | Node nr. | Core | ERAM | TrRx | TrTx | TxHx | IO |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 0 | 5.92 A | 0.14 A | 0.50 A | 0.14 A | 0.56 A | 0.16 A |\n",
- "| 0 | 1 | 1.88 A | 0.09 A | 0.37 A | 0.07 A | 0.76 A | 0.21 A |\n",
- "| 0 | 2 | 3.80 A | 0.22 A | 0.41 A | 0.03 A | 0.76 A | 0.27 A |\n",
- "| 0 | 3 | 3.51 A | 0.09 A | 0.47 A | 0.19 A | 0.65 A | 0.12 A |\n",
- "| 1 | 0 | 5.92 A | 0.14 A | 0.50 A | 0.14 A | 0.56 A | 0.16 A |\n",
- "| 1 | 1 | 1.88 A | 0.09 A | 0.37 A | 0.07 A | 0.76 A | 0.21 A |\n",
- "| 1 | 2 | 3.80 A | 0.22 A | 0.41 A | 0.03 A | 0.76 A | 0.27 A |\n",
- "| 1 | 3 | 3.51 A | 0.09 A | 0.47 A | 0.07 A | 0.77 A | 0.12 A |\n",
+ "| 0 | 0 | 5.95 A | 0.09 A | 0.40 A | 0.21 A | 0.62 A | 0.19 A |\n",
+ "| 0 | 1 | 1.88 A | 0.11 A | 0.33 A | 57933824.00 A | 0.71 A | 0.20 A |\n",
+ "| 0 | 2 | 3.77 A | 0.17 A | 0.45 A | 0.14 A | 0.74 A | 0.27 A |\n",
+ "| 0 | 3 | 3.62 A | 0.07 A | 0.36 A | 0.13 A | 0.72 A | 0.13 A |\n",
+ "| 1 | 0 | nan A | nan A | nan A | nan A | nan A | nan A |\n",
+ "| 1 | 1 | nan A | nan A | nan A | nan A | nan A | nan A |\n",
+ "| 1 | 2 | nan A | nan A | nan A | nan A | nan A | nan A |\n",
+ "| 1 | 3 | nan A | nan A | nan A | nan A | nan A | nan A |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"FPGA power consumption\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | Node nr. | Core pwr | ERAM pwr | TrRx pwr | TrTx pwr | TxHx pwr | IO pwr | Tot.FPGA |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 0 | 5.6 W | 0.1 W | 0.4 W | 0.1 W | 1.0 W | 0.3 W | 7.6 W |\n",
- "| 0 | 1 | 1.8 W | 0.1 W | 0.3 W | 0.1 W | 1.4 W | 0.4 W | 4.0 W |\n",
- "| 0 | 2 | 3.6 W | 0.2 W | 0.4 W | 0.0 W | 1.4 W | 0.5 W | 6.1 W |\n",
- "| 0 | 3 | 3.3 W | 0.1 W | 0.4 W | 0.2 W | 1.2 W | 0.2 W | 5.4 W |\n",
- "| 1 | 0 | 5.6 W | 0.1 W | 0.4 W | 0.1 W | 1.0 W | 0.3 W | 7.6 W |\n",
- "| 1 | 1 | 1.8 W | 0.1 W | 0.3 W | 0.1 W | 1.4 W | 0.4 W | 4.0 W |\n",
- "| 1 | 2 | 3.6 W | 0.2 W | 0.4 W | 0.0 W | 1.4 W | 0.5 W | 6.1 W |\n",
- "| 1 | 3 | 3.3 W | 0.1 W | 0.4 W | 0.1 W | 1.4 W | 0.2 W | 5.5 W |\n",
+ "| 0 | 0 | 5.6 W | 0.1 W | 0.4 W | 0.2 W | 1.1 W | 0.3 W | 7.7 W |\n",
+ "| 0 | 1 | 1.8 W | 0.1 W | 0.3 W | 52148928.0 W | 1.3 W | 0.4 W | 52148931.8 W |\n",
+ "| 0 | 2 | 3.6 W | 0.2 W | 0.4 W | 0.1 W | 1.3 W | 0.5 W | 6.1 W |\n",
+ "| 0 | 3 | 3.4 W | 0.1 W | 0.3 W | 0.1 W | 1.3 W | 0.2 W | 5.5 W |\n",
+ "| 1 | 0 | nan W | nan W | nan W | nan W | nan W | nan W | nan W |\n",
+ "| 1 | 1 | nan W | nan W | nan W | nan W | nan W | nan W | nan W |\n",
+ "| 1 | 2 | nan W | nan W | nan W | nan W | nan W | nan W | nan W |\n",
+ "| 1 | 3 | nan W | nan W | nan W | nan W | nan W | nan W | nan W |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"Board power supply voltages\n",
@@ -199,31 +142,31 @@
"| BRD nr. | QSFP N01 | QSFP N23 |Switch 1v2|Switch PHY| clk pwr | Tot. BRD |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"| 0 | 3.29 V | 3.29 V | 1.20 V | 1.00 V | 2.50 V | 11.99 V |\n",
- "| 1 | 3.29 V | 3.29 V | 1.20 V | 1.00 V | 2.50 V | 11.98 V |\n",
+ "| 1 | nan V | nan V | nan V | nan V | nan V | nan V |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"Board power supply currents\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | QSFP N01 | QSFP N23 |Switch 1v2|Switch PHY| clk pwr | Tot. BRD |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 1.57 A | 1.27 A | 1.73 A | 0.52 A | 0.93 A | 3.62 A |\n",
- "| 1 | 1.57 A | 1.28 A | 1.73 A | 0.52 A | 0.93 A | 3.62 A |\n",
+ "| 0 | 1.55 A | 1.27 A | 1.75 A | 0.59 A | 0.92 A | 3.50 A |\n",
+ "| 1 | nan A | nan A | nan A | nan A | nan A | nan A |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"Board power supply temperatures, should be < 85°C\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | QSFP N01 | QSFP N23 |Switch 1v2|Switch PHY| clk pwr | Tot. BRD |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 31.44 °C | 36.94 °C | 42.44 °C | 43.00 °C | 39.81 °C | 35.00 °C |\n",
- "| 1 | 31.44 °C | 36.94 °C | 42.44 °C | 43.00 °C | 39.81 °C | 35.00 °C |\n",
+ "| 0 | 33.31 °C | 36.88 °C | 42.88 °C | 43.25 °C | 39.31 °C | 34.75 °C |\n",
+ "| 1 | nan °C | nan °C | nan °C | nan °C | nan °C | nan °C |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"Board power consumption\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | QSFP N01 | QSFP N23 |Switch 1v2|Switch PHY| clk pwr | FPGAs pwr| Tot. BRD |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 5.17 W | 4.19 W | 2.07 W | 0.52 W | 2.33 W | 23.18 W | 43.48 W |\n",
- "| 1 | 5.17 W | 4.19 W | 2.07 W | 0.52 W | 2.33 W | 23.18 W | 43.45 W |\n",
+ "| 0 | 5.10 W | 4.19 W | 2.10 W | 0.59 W | 2.30 W | nan W | 41.98 W |\n",
+ "| 1 | nan W | nan W | nan W | nan W | nan W | nan W | nan W |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n"
]
}
@@ -239,11 +182,11 @@
"for brd_cnt in range(2):\n",
" for node_cnt in range(4):\n",
" stri = \"| {} | {} |\".format(brd_cnt, node_cnt) \n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_CORE_TEMP_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_ERAM_TEMP_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_RXGXB_TEMP_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_HGXB_TEMP_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_PGM_TEMP_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} °C |\".format(unb2c.UNB2_FPGA_POL_CORE_TEMP_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} °C |\".format(unb2c.UNB2_FPGA_POL_ERAM_TEMP_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} °C |\".format(unb2c.UNB2_FPGA_POL_RXGXB_TEMP_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} °C |\".format(unb2c.UNB2_FPGA_POL_HGXB_TEMP_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} °C |\".format(unb2c.UNB2_FPGA_POL_PGM_TEMP_R[brd_cnt][node_cnt])\n",
" print(stri)\n",
"print(\"|---------|----------|----------|----------|----------|----------|----------|\\n\")\n",
"if 1:\n",
@@ -259,11 +202,11 @@
" for node_cnt in range(4):\n",
" stri = \"| {} | {} |\".format(brd_cnt, node_cnt)\n",
" stri +=\" {:5.2f} V |\".format(0.95)\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_ERAM_VOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_RXGXB_VOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_TXGXB_VOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_HGXB_VOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_PGM_VOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_ERAM_VOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_RXGXB_VOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_TXGXB_VOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_HGXB_VOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_PGM_VOUT_R[brd_cnt][node_cnt])\n",
" print(stri)\n",
" print(\"|---------|----------|----------|----------|----------|----------|----------|----------|\\n\")\n",
" #\n",
@@ -277,12 +220,12 @@
" fpgas_pwr = np.zeros(2)\n",
" for node_cnt in range(4):\n",
" stri = \"| {} | {} |\".format(brd_cnt, node_cnt)\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_CORE_IOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_ERAM_IOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_RXGXB_IOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_TXGXB_IOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_HGXB_IOUT_R[(brd_cnt*4) + node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_PGM_IOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_CORE_IOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_ERAM_IOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_RXGXB_IOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_TXGXB_IOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_HGXB_IOUT_R[brd_cnt][node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_PGM_IOUT_R[brd_cnt][node_cnt])\n",
" print(stri)\n",
" print(\"|---------|----------|----------|----------|----------|----------|----------|----------|\\n\")\n",
"#\n",
@@ -296,17 +239,17 @@
" fpgas_pwr = np.zeros(2)\n",
" for node_cnt in range(4):\n",
" stri = \"| {} | {} |\".format(brd_cnt, node_cnt)\n",
- " core_pwr = 0.95 * unb2c.UNB2_FPGA_POL_CORE_IOUT_R[(brd_cnt*4) + node_cnt]\n",
+ " core_pwr = 0.95 * unb2c.UNB2_FPGA_POL_CORE_IOUT_R[brd_cnt][node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(core_pwr)\n",
- " eram_pwr = unb2c.UNB2_FPGA_POL_ERAM_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_ERAM_IOUT_R[(brd_cnt*4) + node_cnt]\n",
+ " eram_pwr = unb2c.UNB2_FPGA_POL_ERAM_VOUT_R[brd_cnt][node_cnt]*unb2c.UNB2_FPGA_POL_ERAM_IOUT_R[brd_cnt][node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(eram_pwr)\n",
- " rxgxb_pwr = unb2c.UNB2_FPGA_POL_RXGXB_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_RXGXB_IOUT_R[(brd_cnt*4) + node_cnt]\n",
+ " rxgxb_pwr = unb2c.UNB2_FPGA_POL_RXGXB_VOUT_R[brd_cnt][node_cnt]*unb2c.UNB2_FPGA_POL_RXGXB_IOUT_R[brd_cnt][node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(rxgxb_pwr)\n",
- " txgxb_pwr = unb2c.UNB2_FPGA_POL_TXGXB_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_TXGXB_IOUT_R[(brd_cnt*4) + node_cnt]\n",
+ " txgxb_pwr = unb2c.UNB2_FPGA_POL_TXGXB_VOUT_R[brd_cnt][node_cnt]*unb2c.UNB2_FPGA_POL_TXGXB_IOUT_R[brd_cnt][node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(txgxb_pwr)\n",
- " hgxb_pwre = unb2c.UNB2_FPGA_POL_HGXB_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_HGXB_IOUT_R[(brd_cnt*4) + node_cnt]\n",
+ " hgxb_pwre = unb2c.UNB2_FPGA_POL_HGXB_VOUT_R[brd_cnt][node_cnt]*unb2c.UNB2_FPGA_POL_HGXB_IOUT_R[brd_cnt][node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(hgxb_pwre)\n",
- " pgm_pwr = unb2c.UNB2_FPGA_POL_PGM_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_PGM_IOUT_R[(brd_cnt*4) + node_cnt]\n",
+ " pgm_pwr = unb2c.UNB2_FPGA_POL_PGM_VOUT_R[brd_cnt][node_cnt]*unb2c.UNB2_FPGA_POL_PGM_IOUT_R[brd_cnt][node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(pgm_pwr)\n",
" tot_fpga = core_pwr + eram_pwr + rxgxb_pwr + txgxb_pwr + hgxb_pwre + pgm_pwr\n",
" fpgas_pwr += tot_fpga\n",
@@ -398,9 +341,91 @@
},
{
"cell_type": "code",
- "execution_count": null,
+ "execution_count": 75,
"id": "7f18e187",
"metadata": {},
+ "outputs": [
+ {
+ "name": "stderr",
+ "output_type": "stream",
+ "text": [
+ "Requested secure channel timeout to be 3600000ms, got 600000ms instead\n"
+ ]
+ },
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "Connected to 10.99.0.252:4840\n",
+ "|------+---------------+------|\n",
+ "| Node | FW Version | Temp |\n",
+ "|------+---------------+------|\n",
+ "| 0 | unb2c_minimal |31.4°C|\n",
+ "| 1 | unb2c_minimal |31.4°C|\n",
+ "| 2 | unb2c_minimal |36.2°C|\n",
+ "| 3 | unb2c_minimal |22.6°C|\n",
+ "|------+---------------+------|\n",
+ "[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]\n",
+ "\n",
+ "disconnect from server\n"
+ ]
+ }
+ ],
+ "source": [
+ "#\n",
+ "# Direct access to OPC-UA server on UniBoard2 firmare\n",
+ "#\n",
+ "from opcua import Client\n",
+ "from opcua import ua\n",
+ "host = \"10.99.0.252\"\n",
+ "port = \"4840\"\n",
+ "client = Client(\"opc.tcp://{}:{}/\".format(host, port))\n",
+ "try:\n",
+ " client.connect()\n",
+ " print(\"Connected to {}:{}\".format(host, port))\n",
+ " Object = client.get_objects_node()\n",
+ " children = Object.get_children()\n",
+ "# \n",
+ "# Set if statement to 1 for a list of all children of the firmware\n",
+ "# set if statement to 0 for a table with firmware and temperatures\n",
+ "#\n",
+ " if 0:\n",
+ " for i in range(len(children)):\n",
+ " browse_name = children[i].get_browse_name().to_string()\n",
+ " print(\"\\t\\tchild\", i, \": \", browse_name)\n",
+ " if browse_name in ['0:Server', '0:Aliases']:\n",
+ " continue\n",
+ "# print(\"\\t\\tchild\", i, \": \", children[i].get_array_dimensions())\n",
+ "# print(\"\\t\\tchild\", i, \": \", children[i].get_data_type_as_variant_type())\n",
+ "# print(\"\\t\\tchild\", i, \": \", children[i].get_node_class())\n",
+ " else:\n",
+ " var = Object.get_child(\"2:FPGA_temp_R\")\n",
+ " fpga_temps = var.get_value()\n",
+ " var = Object.get_child(\"2:FPGA_firmware_version_R\")\n",
+ " fpga_versions = var.get_value()\n",
+ " print(\"|------+---------------+------|\")\n",
+ " print(\"| Node | FW Version | Temp |\")\n",
+ " print(\"|------+---------------+------|\")\n",
+ " for node_cnt in range(4):\n",
+ " stri = \"| {} | {} |{:4.1f}°C|\".format(node_cnt, fpga_versions[node_cnt][-13:], fpga_temps[node_cnt])\n",
+ " print(stri)\n",
+ " print(\"|------+---------------+------|\")\n",
+ " var = Object.get_child(\"2:FPGA_jesd204b_csr_dev_syncn_R\")\n",
+ " adc_lock = var.get_value()\n",
+ " print(adc_lock[:32])\n",
+ "\n",
+ "except:\n",
+ " print(\"Connection failed, not connected\")\n",
+ "finally:\n",
+ " print(\"\\ndisconnect from server\")\n",
+ " client.disconnect()\n"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "id": "228b4c23",
+ "metadata": {},
"outputs": [],
"source": []
}
--
GitLab