From 4e6ac599475d4be0b9c6c1766cae7a3c2eca576f Mon Sep 17 00:00:00 2001
From: Gijs Schoonderbeek <schoonderbeek@astron.nl>
Date: Thu, 23 Feb 2023 13:18:25 +0100
Subject: [PATCH] PLL lock is working on HW

---
 apsct_lib.py | 44 +++++++++++++++++++++-----------------------
 1 file changed, 21 insertions(+), 23 deletions(-)

diff --git a/apsct_lib.py b/apsct_lib.py
index 90140c2..47e5d96 100644
--- a/apsct_lib.py
+++ b/apsct_lib.py
@@ -196,7 +196,7 @@ class PllClass:
         write_data = 0x02 | (1 << APSCT_I2C.CS) | (0 << APSCT_I2C.SCLK) | (0 << APSCT_I2C.SDI)
         self.dev_i2c_pll.write_bytes(0x02, write_data)
 
-    def read_byte_pll(self, reg_address, nof_bytes=1):
+    def read_byte_pll(self, reg_address, nof_bytes=1, print_value=False):
         #
         # Read byte from the PLL
         #
@@ -213,11 +213,8 @@ class PllClass:
         for bit in bit_array:
             for clk in [0,1,0]: 
                 write_data = 0x02 | (0 << APSCT_I2C.CS) | (clk << APSCT_I2C.SCLK) | (int(bit) << APSCT_I2C.SDI)
-                print(f"Write data to IO {write_data:08b}")
                 self.dev_i2c_pll.write_bytes(0x02, write_data)
                 sleep(sleep_time)
-#        write_data = 0x02 | (0 << APSCT_I2C.CS) | (0 << APSCT_I2C.SCLK) | (0 << APSCT_I2C.SDI)
-#        self.dev_i2c_pll.write_bytes(0x02, write_data)
         self.dev_i2c_pll.write_bytes(0x06, 0xAC)
         for cnt in range(8*nof_bytes):
             for clk in [0, 1]: #[0, 1, 0]:  # Read after rizing edge
@@ -229,7 +226,8 @@ class PllClass:
                 read_bit += str((int(ret_value, 16) >> APSCT_I2C.SDO) & 0x01)
             else:
                 print("ACK nok")
-        print(f"Read bits {read_bit}")
+        if print_value:
+            print(f"Read bits {read_bit}")
         self.dev_i2c_pll.write_bytes(0x06, 0x2C)
         write_data = 0x02 | (1 << APSCT_I2C.CS) | (0 << APSCT_I2C.SCLK) | (0 << APSCT_I2C.SDI)
         self.dev_i2c_pll.write_bytes(0x02, write_data)
@@ -237,7 +235,7 @@ class PllClass:
             stri = "Read back at address 0x{0:{fill}2x} result : 0x{1:{fill}2x} ".format(reg_address,
                                                                                          int(read_bit, 2), fill='0')
             print(stri)
-        return read_bit
+        return int(read_bit, 2)
 
     def setup_pll(self):
         #
@@ -245,24 +243,27 @@ class PllClass:
         #
         print(f"Setup PPL {self.frequency}")
         divider_r = 1
-        divider_a = 0
-        divider_p = 2
+        divider_a = 1
+        divider_p = 1
         divider_b = int((int(self.frequency[:-3]) * divider_r) / (10 * divider_p))
+        print(f"Divider P : {divider_p}, Divider A : {divider_a}, Divider B : {divider_b}")
         charge_pump_current = 3  # 0 is low (0.6 mA), 7 is high (4.8 mA)
         if self.frequency == '160MHz':
+            print("Select 160MHz clock")
             i2c_address = APSCT_I2C.PLL_200M
             dev_i2c_pll_sel = I2C(i2c_address, BUSNR=I2CBUSNR)
             dev_i2c_pll_sel.write_bytes(0x03, 0x08)
         else:
             self.dev_i2c_pll.write_bytes(0x03, 0x28)
-        self.write_byte_pll(0x04, (divider_a & 0x3F))
+        self.write_byte_pll(0x04, 1) #(divider_a & 0x3F))
         self.write_byte_pll(0x05, (divider_b & 0x1F00) >> 8)
         self.write_byte_pll(0x06, (divider_b & 0x00FF))
-        self.write_byte_pll(0x07, 0x04)  # Lock detect
-        self.write_byte_pll(0x08, 0x03)  # Charge pump normal + Status bit
+        self.write_byte_pll(0x07, 0x00)  # No LOR
+        self.write_byte_pll(0x08, 0x3B)  # Charge pump normal + Status bit
         self.write_byte_pll(0x09, (charge_pump_current & 0x7) << 4)
-        self.write_byte_pll(0x0A, 0x04)  # Fixed Divide 2
+        self.write_byte_pll(0x0A, 0x00)  # Fixed Divide 1
         self.write_byte_pll(0x0B, 0x00)
+        self.write_byte_pll(0x0C, 0x01)
         self.write_byte_pll(0x45, 0x00)  # CLK2 as feedback clock input
         self.write_byte_pll(0x3D, 0x08)  # OUT0 ON LVDS Standard
         self.write_byte_pll(0x3E, 0x0A)  # OUT1 OFF
@@ -274,7 +275,7 @@ class PllClass:
         self.write_byte_pll(0x4F, 0x80)  # OUT2 bypass divider
         self.write_byte_pll(0x51, 0x80)  # OUT3 bypass divider
         self.write_byte_pll(0x53, 0x80)  # OUT4 bypass divider
-        self.write_byte_pll(0x5A, 0x01)  # Update registers
+        self.write_byte_pll(0x5A, 0x0F)  # Update registers
 
 
     def read_all_regs_pll(self):
@@ -282,10 +283,9 @@ class PllClass:
         # Read all registers on the PLL and print on screen
         #
         bytes_to_read = 90
-        ret_value = self.read_byte_pll(0, nof_bytes=bytes_to_read)
         for cnt in range(bytes_to_read):
-            start = cnt*8
-            stri = "Reg nr 0x{:0>2x} value: 0x{:0>2x}".format(cnt, int(ret_value[start:start+8], 2))
+            ret_value = self.read_byte_pll(cnt, 1)
+            stri = f"Reg nr 0x{cnt:0>2x} value: 0x{ret_value:0>2x}"
             print(stri)
 
     def read_lock(self, print_on=True):
@@ -648,19 +648,17 @@ class ApsctId:
 
 def main():
     apsct = ApsctClass()
-    apsct.power(False)
-    sleep(1)
+    if False:
+        apsct.power(False)
+        sleep(1)
     apsct.power(True)
     sleep(1)
     if False:
-#        apsct.pll_200.reset_interface()
         apsct.pll_200.write_byte_pll(0x06, 0xA5)
         apsct.pll_200.write_byte_pll(0x5A, 0x01)
-#        apsct.pll_200.reset_interface()
-        apsct.pll_200.read_byte_pll(0x06)
     apsct.pll_200.setup_pll()
-    apsct.pll_200.read_byte_pll(0x0A)
-    apsct.sensors.read_all_voltages()
+#    apsct.pll_200.read_all_regs_pll()
+#    apsct.sensors.read_all_voltages()
 
 if __name__ == "__main__":
     main()
-- 
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