diff --git a/Jupyter_Pages/UNB2C_HW_Monitor.ipynb b/Jupyter_Pages/UNB2C_HW_Monitor.ipynb
index 8dcc499034274ccae9e3d26813748e2f0ce6d5fc..d2607f6c27f60d6c250140b9752dfb449b0ccdfa 100644
--- a/Jupyter_Pages/UNB2C_HW_Monitor.ipynb
+++ b/Jupyter_Pages/UNB2C_HW_Monitor.ipynb
@@ -11,7 +11,18 @@
},
{
"cell_type": "code",
- "execution_count": 170,
+ "execution_count": 1,
+ "id": "c2ace952",
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import time\n",
+ "import numpy as np"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
"id": "dd54c19e",
"metadata": {
"scrolled": true
@@ -25,48 +36,60 @@
"Atttibutes of pcc are: \n",
"*********\n",
"version_R\n",
- "UNB2_Power_ON_OFF_RW\n",
- "UNB2_Front_Panel_LED_RW\n",
- "UNB2_Front_Panel_LED_R\n",
- "UNB2_mask_RW\n",
- "UNB2_I2C_bus_STATUS_R\n",
- "UNB2_EEPROM_Unique_ID_R\n",
- "UNB2_DC_DC_48V_12V_VIN_R\n",
- "UNB2_DC_DC_48V_12V_VOUT_R\n",
+ "opcua_missing_attributes_R\n",
+ "UNB2TR_translator_busy_R\n",
"UNB2_DC_DC_48V_12V_IOUT_R\n",
"UNB2_DC_DC_48V_12V_TEMP_R\n",
- "UNB2_POL_QSFP_N01_VOUT_R\n",
- "UNB2_POL_QSFP_N01_IOUT_R\n",
- "UNB2_POL_QSFP_N01_TEMP_R\n",
- "UNB2_POL_QSFP_N23_VOUT_R\n",
- "UNB2_POL_QSFP_N23_IOUT_R\n",
- "UNB2_POL_QSFP_N23_TEMP_R\n",
- "UNB2_POL_SWITCH_1V2_VOUT_R\n",
- "UNB2_POL_SWITCH_1V2_IOUT_R\n",
- "UNB2_POL_SWITCH_1V2_TEMP_R\n",
- "UNB2_POL_SWITCH_PHY_VOUT_R\n",
- "UNB2_POL_SWITCH_PHY_IOUT_R\n",
- "UNB2_POL_SWITCH_PHY_TEMP_R\n",
- "UNB2_POL_CLOCK_VOUT_R\n",
- "UNB2_POL_CLOCK_IOUT_R\n",
- "UNB2_POL_CLOCK_TEMP_R\n",
+ "UNB2_DC_DC_48V_12V_VIN_R\n",
+ "UNB2_DC_DC_48V_12V_VOUT_R\n",
+ "UNB2_EEPROM_Serial_Number_R\n",
+ "UNB2_EEPROM_Unique_ID_R\n",
"UNB2_FPGA_DDR4_SLOT_TEMP_R\n",
"UNB2_FPGA_POL_CORE_IOUT_R\n",
"UNB2_FPGA_POL_CORE_TEMP_R\n",
- "UNB2_FPGA_POL_ERAM_VOUT_R\n",
+ "UNB2_FPGA_POL_CORE_VOUT_R\n",
"UNB2_FPGA_POL_ERAM_IOUT_R\n",
"UNB2_FPGA_POL_ERAM_TEMP_R\n",
- "UNB2_FPGA_POL_RXGXB_VOUT_R\n",
- "UNB2_FPGA_POL_RXGXB_IOUT_R\n",
- "UNB2_FPGA_POL_RXGXB_TEMP_R\n",
- "UNB2_FPGA_POL_TXGXB_VOUT_R\n",
- "UNB2_FPGA_POL_TXGXB_IOUT_R\n",
- "UNB2_FPGA_POL_HGXB_VOUT_R\n",
+ "UNB2_FPGA_POL_ERAM_VOUT_R\n",
"UNB2_FPGA_POL_HGXB_IOUT_R\n",
"UNB2_FPGA_POL_HGXB_TEMP_R\n",
- "UNB2_FPGA_POL_PGM_VOUT_R\n",
+ "UNB2_FPGA_POL_HGXB_VOUT_R\n",
"UNB2_FPGA_POL_PGM_IOUT_R\n",
"UNB2_FPGA_POL_PGM_TEMP_R\n",
+ "UNB2_FPGA_POL_PGM_VOUT_R\n",
+ "UNB2_FPGA_POL_RXGXB_IOUT_R\n",
+ "UNB2_FPGA_POL_RXGXB_TEMP_R\n",
+ "UNB2_FPGA_POL_RXGXB_VOUT_R\n",
+ "UNB2_FPGA_POL_TXGXB_IOUT_R\n",
+ "UNB2_FPGA_POL_TXGXB_TEMP_R\n",
+ "UNB2_FPGA_POL_TXGXB_VOUT_R\n",
+ "UNB2_FPGA_QSFP_CAGE_LOS_R\n",
+ "UNB2_FPGA_QSFP_CAGE_TEMP_R\n",
+ "UNB2_Front_Panel_LED_R\n",
+ "UNB2_Front_Panel_LED_RW\n",
+ "UNB2_I2C_bus_DDR4_error_R\n",
+ "UNB2_I2C_bus_error_R\n",
+ "UNB2_I2C_bus_FPGA_PS_error_R\n",
+ "UNB2_I2C_bus_PS_error_R\n",
+ "UNB2_I2C_bus_QSFP_error_R\n",
+ "UNB2_mask_RW\n",
+ "UNB2_POL_CLOCK_IOUT_R\n",
+ "UNB2_POL_CLOCK_TEMP_R\n",
+ "UNB2_POL_CLOCK_VOUT_R\n",
+ "UNB2_POL_QSFP_N01_IOUT_R\n",
+ "UNB2_POL_QSFP_N01_TEMP_R\n",
+ "UNB2_POL_QSFP_N01_VOUT_R\n",
+ "UNB2_POL_QSFP_N23_IOUT_R\n",
+ "UNB2_POL_QSFP_N23_TEMP_R\n",
+ "UNB2_POL_QSFP_N23_VOUT_R\n",
+ "UNB2_POL_SWITCH_1V2_IOUT_R\n",
+ "UNB2_POL_SWITCH_1V2_TEMP_R\n",
+ "UNB2_POL_SWITCH_1V2_VOUT_R\n",
+ "UNB2_POL_SWITCH_PHY_IOUT_R\n",
+ "UNB2_POL_SWITCH_PHY_TEMP_R\n",
+ "UNB2_POL_SWITCH_PHY_VOUT_R\n",
+ "UNB2_PWR_off_R\n",
+ "UNB2_PWR_off_RW\n",
"State\n",
"Status\n",
"*********\n",
@@ -78,7 +101,7 @@
"#\n",
"# Check is device is running or else start it up\n",
"#\n",
- "unb2c=DeviceProxy(\"LTS/UNB2/1\")\n",
+ "unb2c = DeviceProxy(\"LTS/UNB2/1\")\n",
"state = str(unb2c.state())\n",
"\n",
"if state == \"OFF\" or state == \"FAULT\":\n",
@@ -105,7 +128,7 @@
},
{
"cell_type": "code",
- "execution_count": 174,
+ "execution_count": 10,
"id": "51d0443c",
"metadata": {
"scrolled": true
@@ -119,14 +142,14 @@
"|---------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | Node nr. | Core pol | ERAM pol | TrRx pol | TxHx pol | IO pol |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 0 | 28.9 °C | 36.1 °C | 32.1 °C | 37.8 °C | 37.4 °C |\n",
- "| 0 | 1 | 29.5 °C | 36.8 °C | 34.9 °C | 39.0 °C | 39.8 °C |\n",
- "| 0 | 2 | 30.4 °C | 38.6 °C | 33.4 °C | 41.4 °C | 41.4 °C |\n",
- "| 0 | 3 | 32.8 °C | 38.8 °C | 34.9 °C | 38.2 °C | 37.8 °C |\n",
- "| 1 | 0 | 28.9 °C | 36.1 °C | 32.1 °C | 37.8 °C | 37.4 °C |\n",
- "| 1 | 1 | 29.5 °C | 36.8 °C | 34.9 °C | 39.0 °C | 39.8 °C |\n",
- "| 1 | 2 | 30.4 °C | 38.6 °C | 33.4 °C | 41.4 °C | 41.4 °C |\n",
- "| 1 | 3 | 32.8 °C | 38.8 °C | 34.9 °C | 38.2 °C | 37.8 °C |\n",
+ "| 0 | 0 | 30.2 °C | 36.2 °C | 32.6 °C | 36.9 °C | 38.8 °C |\n",
+ "| 0 | 1 | 31.5 °C | 37.4 °C | 35.4 °C | 40.3 °C | 41.4 °C |\n",
+ "| 0 | 2 | 30.2 °C | 38.4 °C | 33.6 °C | 40.8 °C | 42.1 °C |\n",
+ "| 0 | 3 | 31.5 °C | 39.0 °C | 34.6 °C | 38.6 °C | 38.1 °C |\n",
+ "| 1 | 0 | 30.2 °C | 36.2 °C | 32.6 °C | 36.9 °C | 38.8 °C |\n",
+ "| 1 | 1 | 31.5 °C | 37.4 °C | 35.4 °C | 40.3 °C | 41.4 °C |\n",
+ "| 1 | 2 | 30.2 °C | 38.4 °C | 33.6 °C | 40.8 °C | 42.1 °C |\n",
+ "| 1 | 3 | 31.5 °C | 39.0 °C | 34.6 °C | 38.2 °C | 38.1 °C |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"FPGA point-of-load converte voltages\n",
@@ -147,28 +170,28 @@
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | Node nr. | Core | ERAM | TrRx | TrTx | TxHx | IO |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 0 | 5.95 A | 0.09 A | 0.40 A | 0.06 A | 0.61 A | 0.22 A |\n",
- "| 0 | 1 | 4.16 A | 0.09 A | 0.41 A | 0.08 A | 0.72 A | 0.21 A |\n",
- "| 0 | 2 | 3.81 A | 0.13 A | 0.48 A | 0.04 A | 0.73 A | 0.17 A |\n",
- "| 0 | 3 | 3.61 A | 0.14 A | 0.41 A | 0.14 A | 0.73 A | 0.13 A |\n",
- "| 1 | 0 | 5.95 A | 0.09 A | 0.40 A | 0.06 A | 0.61 A | 0.22 A |\n",
- "| 1 | 1 | 4.16 A | 0.09 A | 0.41 A | 0.08 A | 0.72 A | 0.21 A |\n",
- "| 1 | 2 | 3.81 A | 0.13 A | 0.48 A | 0.04 A | 0.73 A | 0.17 A |\n",
- "| 1 | 3 | 3.61 A | 0.14 A | 0.41 A | 0.14 A | 0.73 A | 0.13 A |\n",
+ "| 0 | 0 | 5.92 A | 0.14 A | 0.50 A | 0.14 A | 0.56 A | 0.16 A |\n",
+ "| 0 | 1 | 1.88 A | 0.09 A | 0.37 A | 0.07 A | 0.76 A | 0.21 A |\n",
+ "| 0 | 2 | 3.80 A | 0.22 A | 0.41 A | 0.03 A | 0.76 A | 0.27 A |\n",
+ "| 0 | 3 | 3.51 A | 0.09 A | 0.47 A | 0.19 A | 0.65 A | 0.12 A |\n",
+ "| 1 | 0 | 5.92 A | 0.14 A | 0.50 A | 0.14 A | 0.56 A | 0.16 A |\n",
+ "| 1 | 1 | 1.88 A | 0.09 A | 0.37 A | 0.07 A | 0.76 A | 0.21 A |\n",
+ "| 1 | 2 | 3.80 A | 0.22 A | 0.41 A | 0.03 A | 0.76 A | 0.27 A |\n",
+ "| 1 | 3 | 3.51 A | 0.09 A | 0.47 A | 0.07 A | 0.77 A | 0.12 A |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"FPGA power consumption\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | Node nr. | Core pwr | ERAM pwr | TrRx pwr | TrTx pwr | TxHx pwr | IO pwr | Tot.FPGA |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 0 | 5.7 W | 0.1 W | 0.4 W | 0.1 W | 1.1 W | 0.4 W | 7.6 W |\n",
- "| 0 | 1 | 4.0 W | 0.1 W | 0.4 W | 0.1 W | 1.3 W | 0.4 W | 6.1 W |\n",
- "| 0 | 2 | 3.6 W | 0.1 W | 0.4 W | 0.0 W | 1.3 W | 0.3 W | 5.8 W |\n",
- "| 0 | 3 | 3.4 W | 0.1 W | 0.4 W | 0.1 W | 1.3 W | 0.2 W | 5.6 W |\n",
- "| 1 | 0 | 5.7 W | 0.1 W | 0.4 W | 0.1 W | 1.1 W | 0.4 W | 7.6 W |\n",
- "| 1 | 1 | 4.0 W | 0.1 W | 0.3 W | 0.1 W | 1.3 W | 0.4 W | 6.1 W |\n",
- "| 1 | 2 | 3.6 W | 0.1 W | 0.4 W | 0.1 W | 1.3 W | 0.5 W | 5.9 W |\n",
- "| 1 | 3 | 3.4 W | 0.1 W | 0.4 W | 0.1 W | 1.3 W | 0.2 W | 5.5 W |\n",
+ "| 0 | 0 | 5.6 W | 0.1 W | 0.4 W | 0.1 W | 1.0 W | 0.3 W | 7.6 W |\n",
+ "| 0 | 1 | 1.8 W | 0.1 W | 0.3 W | 0.1 W | 1.4 W | 0.4 W | 4.0 W |\n",
+ "| 0 | 2 | 3.6 W | 0.2 W | 0.4 W | 0.0 W | 1.4 W | 0.5 W | 6.1 W |\n",
+ "| 0 | 3 | 3.3 W | 0.1 W | 0.4 W | 0.2 W | 1.2 W | 0.2 W | 5.4 W |\n",
+ "| 1 | 0 | 5.6 W | 0.1 W | 0.4 W | 0.1 W | 1.0 W | 0.3 W | 7.6 W |\n",
+ "| 1 | 1 | 1.8 W | 0.1 W | 0.3 W | 0.1 W | 1.4 W | 0.4 W | 4.0 W |\n",
+ "| 1 | 2 | 3.6 W | 0.2 W | 0.4 W | 0.0 W | 1.4 W | 0.5 W | 6.1 W |\n",
+ "| 1 | 3 | 3.3 W | 0.1 W | 0.4 W | 0.1 W | 1.4 W | 0.2 W | 5.5 W |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"Board power supply voltages\n",
@@ -176,31 +199,31 @@
"| BRD nr. | QSFP N01 | QSFP N23 |Switch 1v2|Switch PHY| clk pwr | Tot. BRD |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"| 0 | 3.29 V | 3.29 V | 1.20 V | 1.00 V | 2.50 V | 11.99 V |\n",
- "| 1 | 3.29 V | 3.29 V | 1.20 V | 1.00 V | 2.50 V | 11.99 V |\n",
+ "| 1 | 3.29 V | 3.29 V | 1.20 V | 1.00 V | 2.50 V | 11.98 V |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"Board power supply currents\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | QSFP N01 | QSFP N23 |Switch 1v2|Switch PHY| clk pwr | Tot. BRD |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 1.53 A | 1.27 A | 1.60 A | 0.50 A | 0.84 A | 3.50 A |\n",
- "| 1 | 1.53 A | 1.27 A | 1.60 A | 0.50 A | 0.84 A | 3.62 A |\n",
+ "| 0 | 1.57 A | 1.27 A | 1.73 A | 0.52 A | 0.93 A | 3.62 A |\n",
+ "| 1 | 1.57 A | 1.28 A | 1.73 A | 0.52 A | 0.93 A | 3.62 A |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"Board power supply temperatures, should be < 85°C\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | QSFP N01 | QSFP N23 |Switch 1v2|Switch PHY| clk pwr | Tot. BRD |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 31.44 °C | 36.94 °C | 41.94 °C | 43.50 °C | 40.50 °C | 34.50 °C |\n",
- "| 1 | 31.44 °C | 36.94 °C | 41.94 °C | 43.50 °C | 40.50 °C | 34.50 °C |\n",
+ "| 0 | 31.44 °C | 36.94 °C | 42.44 °C | 43.00 °C | 39.81 °C | 35.00 °C |\n",
+ "| 1 | 31.44 °C | 36.94 °C | 42.44 °C | 43.00 °C | 39.81 °C | 35.00 °C |\n",
"|---------|----------|----------|----------|----------|----------|----------|\n",
"\n",
"Board power consumption\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
"| BRD nr. | QSFP N01 | QSFP N23 |Switch 1v2|Switch PHY| clk pwr | FPGAs pwr| Tot. BRD |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n",
- "| 0 | 5.03 W | 4.18 W | 1.86 W | 0.43 W | 2.48 W | 25.21 W | 43.46 W |\n",
- "| 1 | 5.03 W | 4.18 W | 1.86 W | 0.43 W | 2.48 W | 25.21 W | 43.46 W |\n",
+ "| 0 | 5.17 W | 4.19 W | 2.07 W | 0.52 W | 2.33 W | 23.18 W | 43.48 W |\n",
+ "| 1 | 5.17 W | 4.19 W | 2.07 W | 0.52 W | 2.33 W | 23.18 W | 43.45 W |\n",
"|---------|----------|----------|----------|----------|----------|----------|----------|\n"
]
}
@@ -216,11 +239,11 @@
"for brd_cnt in range(2):\n",
" for node_cnt in range(4):\n",
" stri = \"| {} | {} |\".format(brd_cnt, node_cnt) \n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_CORE_TEMP_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_ERAM_TEMP_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_RXGXB_TEMP_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_HGXB_TEMP_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_PGM_TEMP_R[brd_cnt,node_cnt])\n",
+ " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_CORE_TEMP_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_ERAM_TEMP_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_RXGXB_TEMP_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_HGXB_TEMP_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.1f} °C |\".format(unb2c.UNB2_FPGA_POL_PGM_TEMP_R[(brd_cnt*4) + node_cnt])\n",
" print(stri)\n",
"print(\"|---------|----------|----------|----------|----------|----------|----------|\\n\")\n",
"if 1:\n",
@@ -236,11 +259,11 @@
" for node_cnt in range(4):\n",
" stri = \"| {} | {} |\".format(brd_cnt, node_cnt)\n",
" stri +=\" {:5.2f} V |\".format(0.95)\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_ERAM_VOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_RXGXB_VOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_TXGXB_VOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_HGXB_VOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_PGM_VOUT_R[brd_cnt,node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_ERAM_VOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_RXGXB_VOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_TXGXB_VOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_HGXB_VOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} V |\".format(unb2c.UNB2_FPGA_POL_PGM_VOUT_R[(brd_cnt*4) + node_cnt])\n",
" print(stri)\n",
" print(\"|---------|----------|----------|----------|----------|----------|----------|----------|\\n\")\n",
" #\n",
@@ -254,12 +277,12 @@
" fpgas_pwr = np.zeros(2)\n",
" for node_cnt in range(4):\n",
" stri = \"| {} | {} |\".format(brd_cnt, node_cnt)\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_CORE_IOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_ERAM_IOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_RXGXB_IOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_TXGXB_IOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_HGXB_IOUT_R[brd_cnt,node_cnt])\n",
- " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_PGM_IOUT_R[brd_cnt,node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_CORE_IOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_ERAM_IOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_RXGXB_IOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_TXGXB_IOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_HGXB_IOUT_R[(brd_cnt*4) + node_cnt])\n",
+ " stri +=\" {:5.2f} A |\".format(unb2c.UNB2_FPGA_POL_PGM_IOUT_R[(brd_cnt*4) + node_cnt])\n",
" print(stri)\n",
" print(\"|---------|----------|----------|----------|----------|----------|----------|----------|\\n\")\n",
"#\n",
@@ -273,17 +296,17 @@
" fpgas_pwr = np.zeros(2)\n",
" for node_cnt in range(4):\n",
" stri = \"| {} | {} |\".format(brd_cnt, node_cnt)\n",
- " core_pwr = 0.95 * unb2c.UNB2_FPGA_POL_CORE_IOUT_R[brd_cnt,node_cnt]\n",
+ " core_pwr = 0.95 * unb2c.UNB2_FPGA_POL_CORE_IOUT_R[(brd_cnt*4) + node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(core_pwr)\n",
- " eram_pwr = unb2c.UNB2_FPGA_POL_ERAM_VOUT_R[brd_cnt,node_cnt]*unb2c.UNB2_FPGA_POL_ERAM_IOUT_R[brd_cnt,node_cnt]\n",
+ " eram_pwr = unb2c.UNB2_FPGA_POL_ERAM_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_ERAM_IOUT_R[(brd_cnt*4) + node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(eram_pwr)\n",
- " rxgxb_pwr = unb2c.UNB2_FPGA_POL_RXGXB_VOUT_R[brd_cnt,node_cnt]*unb2c.UNB2_FPGA_POL_RXGXB_IOUT_R[brd_cnt,node_cnt]\n",
+ " rxgxb_pwr = unb2c.UNB2_FPGA_POL_RXGXB_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_RXGXB_IOUT_R[(brd_cnt*4) + node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(rxgxb_pwr)\n",
- " txgxb_pwr = unb2c.UNB2_FPGA_POL_TXGXB_VOUT_R[brd_cnt,node_cnt]*unb2c.UNB2_FPGA_POL_TXGXB_IOUT_R[brd_cnt,node_cnt]\n",
+ " txgxb_pwr = unb2c.UNB2_FPGA_POL_TXGXB_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_TXGXB_IOUT_R[(brd_cnt*4) + node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(txgxb_pwr)\n",
- " hgxb_pwre = unb2c.UNB2_FPGA_POL_HGXB_VOUT_R[brd_cnt,node_cnt]*unb2c.UNB2_FPGA_POL_HGXB_IOUT_R[brd_cnt,node_cnt]\n",
+ " hgxb_pwre = unb2c.UNB2_FPGA_POL_HGXB_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_HGXB_IOUT_R[(brd_cnt*4) + node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(hgxb_pwre)\n",
- " pgm_pwr = unb2c.UNB2_FPGA_POL_PGM_VOUT_R[brd_cnt,node_cnt]*unb2c.UNB2_FPGA_POL_PGM_IOUT_R[brd_cnt,node_cnt]\n",
+ " pgm_pwr = unb2c.UNB2_FPGA_POL_PGM_VOUT_R[(brd_cnt*4) + node_cnt]*unb2c.UNB2_FPGA_POL_PGM_IOUT_R[(brd_cnt*4) + node_cnt]\n",
" stri +=\" {:4.1f} W |\".format(pgm_pwr)\n",
" tot_fpga = core_pwr + eram_pwr + rxgxb_pwr + txgxb_pwr + hgxb_pwre + pgm_pwr\n",
" fpgas_pwr += tot_fpga\n",