diff --git a/config/UNB2.yaml b/config/UNB2.yaml
index 5ac65152df724826fc6d31bd083adf5d8d630d2f..750d31cd440e32c5b297cecffb67e35c2b5e1bca 100644
--- a/config/UNB2.yaml
+++ b/config/UNB2.yaml
@@ -136,7 +136,7 @@ variables:
driver: GPIO
mask: UNB2_mask
width: 1
- rw: ro
+ rw: hidden #ro
dtype: boolean
dim: 2
@@ -155,7 +155,7 @@ variables:
driver: switch_UNB2
devreg: 0x50.0
width: 80 #10 characters
- rw: ro
+ rw: hidden #ro
dtype: string
dim: 2
@@ -167,43 +167,67 @@ variables:
dtype: uint32
dim: 2
- - name: [UNB2_DC_DC_48V_12V_VIN,UNB2_DC_DC_48V_12V_VOUT,UNB2_DC_DC_48V_12V_IOUT,UNB2_DC_DC_48V_12V_TEMP]
+
+ - name: [UNB2_DC_DC_48V_12V_VIN,UNB2_DC_DC_48V_12V_VOUT]
+ driver: switch_PS
+ devreg: [0x2C.0x88,0x2C.0x8B]
+ width: 16
+ rw: ro
+ dtype: double
+ endian: "<"
+ scale: 4.8828125e-4 #2^-11
+ dim: 2
+ monitor: true
+
+ - name: [UNB2_DC_DC_48V_12V_VOUT_MODE,UNB2_POL_QSFP_N01_VOUT_MODE,UNB2_POL_QSFP_N23_VOUT_MODE,UNB2_POL_SWITCH_1V2_VOUT_MODE,UNB2_POL_SWITCH_PHY_VOUT_MODE,UNB2_POL_CLOCK_VOUT_MODE]
+ driver: switch_PS
+ devreg: [0x2C.0x20,0x2.0x20,0x1.0x20,0xF.0x20,0xE.0x20,0xD.0x20]
+ width: 8
+ rw: ro
+ dtype: uint8
+ dim: 2
+ debug: true
+ monitor: true
+
+ - name: [UNB2_POL_QSFP_N01_VOUT,UNB2_POL_QSFP_N23_VOUT]
driver: switch_PS
- devreg: [0x2C.0x88,0x2C.0x8B,0x2C.0x8C,0x2C.0x8D]
+ devreg: [0x2.0x8B,0x1.0x8B]
width: 16
rw: ro
dtype: double
- scale: 1.2207e-4 #2^-13
+ endian: "<"
+ scale: 1.220703125e-4 #2^-13
dim: 2
monitor: true
- - name: [UNB2_POL_QSFP_N01_VOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_VOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_QSFP_N23_TEMP]
+ - name: [UNB2_POL_SWITCH_1V2_VOUT,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_CLOCK_VOUT]
driver: switch_PS
- devreg: [0x2.0x8B,0x2.0x8C,0x2.0x8D,0x1.0x8B,0x1.0x8C,0x1.0x8D]
+ devreg: [0xF.0x8B,0xE.0x8B,0xD.0x8B]
width: 16
rw: ro
dtype: double
- scale: 1.2207e-4 #2^-13
+ endian: "<"
+ scale: 2.44140625e-4 #2^-12
dim: 2
monitor: true
- - name: [UNB2_POL_SWITCH_1V2_VOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_SWITCH_PHY_TEMP]
+ - name: [UNB2_DC_DC_48V_12V_IOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
driver: switch_PS
- devreg: [0xF.0x8B,0xF.0x8C,0xF.0x8D,0xE.0x8B,0xE.0x8C,0xE.0x8D]
+ devreg: [0x2C.0x8C,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
width: 16
rw: ro
dtype: double
- scale: 1.2207e-4 #2^-13
+ scale: smbus_2bytes_to_float
dim: 2
monitor: true
- - name: [UNB2_POL_CLOCK_VOUT,UNB2_POL_CLOCK_IOUT,UNB2_POL_CLOCK_TEMP]
+ - name: [UNB2_DC_DC_48V_12V_TEMP,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_TEMP,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
driver: switch_PS
- devreg: [0xD.0x8B,0xD.0x8C,0xD.0x8D]
+ devreg: [0x2C.0x8D,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
width: 16
rw: ro
dtype: double
- scale: 1.2207e-4 #2^-13
+ scale: smbus_2bytes_to_float
dim: 2
monitor: true
@@ -223,41 +247,62 @@ variables:
driver: switch_DDR4
devreg: [0x18.0x149,0x19.0x149]
width: 160
- rw: ro
+ rw: hidden #ro
dtype: string
dim: 16
+# monitor: true
+
+ - name: [UNB2_FPGA_POL_CORE_IOUT,UNB2_FPGA_POL_ERAM_IOUT,UNB2_FPGA_POL_RXGXB_IOUT,UNB2_FPGA_POL_TXGXB_IOUT,UNB2_FPGA_POL_HGXB_IOUT,UNB2_FPGA_POL_PGM_IOUT]
+ driver: switch_FPGA_PS
+ devreg: [0x1.0x8C,0xD.0x8C,0xE.0x8C,0xF.0x8C,0x10.0x8C,0x11.0x8C]
+ width: 16
+ rw: ro
+ dtype: double
+ scale: smbus_2bytes_to_float
+ dim: 8
monitor: true
- - name: [UNB2_POL_FPGA_CORE_VOUT,UNB2_FPGA_POL_CORE_IOUT,UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_ERAM_IOUT,UNB2_FPGA_POL_ERAM_TEMP]
+ - name: [UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_TEMP,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_TEMP,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_TEMP]
driver: switch_FPGA_PS
- devreg: [0x1.0x8B,0x1.0x8C,0x1.0x8D,0xD.0x8B,0xD.0x8C,0xD.0x8D]
+ devreg: [0x1.0x8D,0xD.0x8D,0xE.0x8D,0xF.0x8D,0x10.0x8D,0x11.0x8D]
width: 16
rw: ro
dtype: double
- scale: 1.2207e-4 #2^-13
+ scale: smbus_2bytes_to_float
dim: 8
monitor: true
- - name: [UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_RXGXB_IOUT,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_TXGXB_IOUT,UNB2_POL_FPGA_TXGXB_TEMP]
+ - name: [UNB2_FPGA_POL_CORE_VOUT]
driver: switch_FPGA_PS
- devreg: [0xE.0x8B,0xE.0x8C,0xE.0x8D,0xF.0x8B,0xF.0x8C,0xF.0x8D]
+ devreg: [0x1.0x8B]
width: 16
rw: ro
dtype: double
- scale: 1.2207e-4 #2^-13
+ endian: "<"
+ scale: 1.220703125e-4 #2^-13
dim: 8
monitor: true
- - name: [UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_HGXB_IOUT,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_VOUT,UNB2_FPGA_POL_PGM_IOUT,UNB2_FPGA_POL_PGM_TEMP]
+ - name: [UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_PGM_VOUT]
driver: switch_FPGA_PS
- devreg: [0x10.0x8B,0x10.0x8C,0x10.0x8D,0x11.0x8B,0x11.0x8C,0x11.0x8D]
+ devreg: [0xD.0x8B,0xE.0x8B,0xF.0x8B,0x10.0x8B,0x11.0x8B]
width: 16
rw: ro
dtype: double
- scale: 1.2207e-4 #2^-13
+ endian: "<"
+ scale: 2.44140625e-4 #2^-12
dim: 8
monitor: true
+ - name: [UNB2_FPGA_POL_CORE_VOUT_MODE,UNB2_FPGA_POL_ERAM_VOUT_MODE,UNB2_FPGA_POL_RXGXB_VOUT_MODE,UNB2_FPGA_POL_TXGXB_VOUT_MODE,UNB2_FPGA_POL_HGXB_VOUT_MODE,UNB2_FPGA_POL_PGM_VOUT_MODE]
+ driver: switch_FPGA_PS
+ devreg: [0x1.0x20,0xD.0x20,0xE.0x20,0xF.0x20,0x10.0x20,0x11.0x20]
+ width: 8
+ rw: ro
+ dtype: uint8
+ dim: 8
+ debug: true
+ monitor: true
##Local MP per FPGA node, QSFP cage
@@ -268,7 +313,7 @@ variables:
width: 16
rw: ro
dtype: double
- scale: 0.0625 #TBC
+ scale: 3.90625e-3 #1/256
dim: 48
monitor: true
@@ -284,6 +329,13 @@ variables:
methods:
+ - name: UNB2_Init #Called after startup to load.
+ driver: switch_UNB2
+ debug: True
+ instructions:
+ - UNB2_EEPROM_Unique_ID: Update
+
+
- name: UNB2_on
mask: UNB2_mask
instructions:
diff --git a/i2cserv/i2c.py b/i2cserv/i2c.py
index 3eb98b2e5b2709666b647b370600ac8f6fc27a61..27e86db37782e13cdf95000b4890a338918a27ec 100644
--- a/i2cserv/i2c.py
+++ b/i2cserv/i2c.py
@@ -32,6 +32,7 @@ class i2c(hwdev):
bus.iaddr_bytes=0
if not(reg is None):
bus.ioctl_write(0,bytes(bytearray([reg])))
+# time.sleep(0.500)
data[:]=[int(x) for x in bus.ioctl_read(0,length)]
logging.debug(str(("I2C get",addr,reg,data,read)))
# print("I2C read",addr,reg,data,read)
diff --git a/i2cserv/i2c_array.py b/i2cserv/i2c_array.py
index 60fed98e8b6247608a9c99ba03605d8a4e7c7696..ce2c610034bd2ee2773e7590a4af97fbbc0e07bb 100644
--- a/i2cserv/i2c_array.py
+++ b/i2cserv/i2c_array.py
@@ -24,6 +24,7 @@ class i2c_array(i2c_dev):
self.RCU_Switch1=range(pars[0],pars[1]+1);
self.N=len(self.RCU_Switch1);
self.I2Cmask=[0]*self.N
+ self.disableI2ConError=True;
# self.devregs,RCU_storeReg=DevRegList(yaml)
# print("Init",config['name'],'len=',len(self.RCU_Switch1),' stored reg=',RCU_storeReg)
@@ -74,14 +75,14 @@ class i2c_array(i2c_dev):
self.RCUi=RCUi;
res=self.SetVarValue(devreg,width,bitoffset,data[i0:i1])
if not(res):
- self.I2Cmask[RCUi]=1;
+ if self.disableI2ConError: self.I2Cmask[RCUi]=1;
mask[RCUi*Step+Vari]=False;
continue;
if getalso:
value2=value1[i0:i1]
res=self.GetVarValue(devreg,width,bitoffset,value2)
if not(res):
- self.I2Cmask[RCUi]=1;
+ if self.disableI2ConError: self.I2Cmask[RCUi]=1;
mask[RCUi*Step+Vari]=False;
continue;
value1[i0:i1]=value2
@@ -116,7 +117,7 @@ class i2c_array(i2c_dev):
self.RCUi=RCUi;
res=self.GetVarValue(devreg,width,bitoffset,value2)
if not(res):
- self.I2Cmask[RCUi]=1;
+ if self.disableI2ConError: self.I2Cmask[RCUi]=1;
mask[RCUi*Step+Vari]=False;
continue;
value1[i0:i1]=value2
@@ -158,7 +159,7 @@ class i2c_array(i2c_dev):
self.RCUi=RCUi;
res=self.GetVarValue(devreg,8,0,value2)
if not(res):
- self.I2Cmask[RCUi]=False;
+ if self.disableI2ConError: self.I2Cmask[RCUi]=1;
value1[RCUi]=value2[0]
if devreg.get('store'):
if mask[RCUi]:
@@ -199,7 +200,7 @@ class i2c_array(i2c_dev):
if not(callback(devreg['addr'],value2,reg=reg,read=1)): return False;
if value2[0] is None: return False
value[:]=value2[:];
- if devreg['store']:
+ if devreg.get('store'):
storearray=self.getstorearray(devreg,len(value));
storearray[self.RCUi]=(value[0] if len(value)==1 else value[:])
logging.debug(str(("Store buffer",self.RCUi,storearray[self.RCUi])))
diff --git a/i2cserv/i2c_array2.py b/i2cserv/i2c_array2.py
index ef71eb3661414a3d1683c74950bf9d82a83dbabf..8a515636fcc0713ca44d78e87a97f464305ea419 100644
--- a/i2cserv/i2c_array2.py
+++ b/i2cserv/i2c_array2.py
@@ -22,6 +22,7 @@ class i2c_array2(i2c_array):
if len(sw2)>0: self.N*=len(sw2)
if len(sw3)>0: self.N*=len(sw3)
self.I2Cmask=[0]*self.N
+ self.disableI2ConError=False;
self.sw1=[x for x in sw1 for i in range(self.N//len(sw1))]
self.sw2=[x for x in sw2 for i in range(self.N//len(sw1)//len(sw2))]*len(sw1)
self.sw3=[x for x in sw3]*len(sw1)*len(sw2)
diff --git a/i2cserv/i2c_smbus.py b/i2cserv/i2c_smbus.py
new file mode 100644
index 0000000000000000000000000000000000000000..a0b6efc03f2ac02a76936632b669500e9ad0ff9c
--- /dev/null
+++ b/i2cserv/i2c_smbus.py
@@ -0,0 +1,60 @@
+import os
+#if os.sys.platform is 'linux':
+#import pylibi2c;
+import smbus
+import time
+import logging
+#read=0: write to register
+#read=1: read from register
+#read=2: write to register (common in group)
+#read=3: wait ms second
+from .hwdev import hwdev;
+
+class i2c_smbus(hwdev):
+ def __init__(self,config):
+ hwdev.__init__(self,config);
+# self.I2Cdev='/dev/i2c-'+str(config['parameters'][0]);
+ self.bus_nr=config['parameters'][0]
+ logging.info("smbus driver on bus "+str(self.bus_nr))
+ self.bus = smbus.SMBus(self.bus_nr)
+ self.I2Ccounter=0
+
+ def i2csetget(self,addr,data,reg=None,read=0):
+ try:
+# if True:
+ if read==3:
+ time.sleep(data[0]/1000.)
+ return True
+# bus=pylibi2c.I2CDevice(self.I2Cdev,addr)
+ length=len(data)
+ if read==1:
+ if not(reg is None):
+ data[:]=self.bus.read_i2c_block_data(addr, reg, length)
+ elif length==1:
+ data[0]=self.bus.read_byte(addr)
+ elif length==2:
+ d=self.bus.read_word(addr)
+ data[0]=(d>>8)&255;
+ data[1]=d&255;
+ else:
+ for i in range(length):
+ data[i]=self.bus.read_byte(addr) #Not vey efficient!!
+ logging.debug(str(("I2C get",addr,reg,data,read)))
+ else:
+ if not(reg is None):
+ self.bus.write_i2c_block_data(addr, reg, data)
+ elif length==1:
+ self.bus.write_byte(addr,data[0])
+ elif length==2:
+ self.bus.write_word(addr,data[0]<<8+data[1])
+ else:
+ for i in range(length):
+ self.bus.write_byte(addr,data[i]) #Not vey efficient!!
+ logging.debug(str(("I2C set",addr,reg,bytes(bytearray(data)),read)))
+ return True;
+ except:
+# else:
+ logging.debug("I2C failed!")
+# data[:]=0
+ return False;
+
diff --git a/i2cserv/i2c_switch2.py b/i2cserv/i2c_switch2.py
index e86b47cff9fa12144433358100be54c006260fb0..4600c0a1b8aaa05d0d76e9cd2916530510814fea 100644
--- a/i2cserv/i2c_switch2.py
+++ b/i2cserv/i2c_switch2.py
@@ -1,6 +1,6 @@
#3 switches of UNB2
import logging
-from .i2c import i2c
+from .i2c_smbus import i2c_smbus as i2c
class i2c_switch2(i2c):
def __init__(self,config):
@@ -8,26 +8,28 @@ class i2c_switch2(i2c):
self.SWaddr1=config['devreg'][0]['addr']
self.SWaddr2=config['devreg'][1]['addr']
self.SWaddr3=config['devreg'][2]['addr']
- self.channel1=0
- self.channel2=0
- self.channel3=0
+ self.channel1=-1
+ self.channel2=-1
+ self.channel3=-1
logging.info("i2c switch2 at address %i,%i,%i" % (self.SWaddr1,self.SWaddr2,self.SWaddr3))
+ logging.warn("APSCT switch disabled for testing")
def SetSW1(self,channelbit):
channel=1<<(channelbit)
if (channel)==self.channel1: return True;
logging.debug("SetChannel1=%i" % channelbit)
self.channel1=channel
- self.channel2=0
- self.channel3=0
- return self.i2csetget(self.SWaddr1,[channel])
+ self.channel2=-1
+ self.channel3=-1
+ return True; #testing without APSCT switch
+# return self.i2csetget(self.SWaddr1,[channel])
def SetSW2(self,channelbit):
channel=1<<(channelbit)
if (channel)==self.channel2: return True;
logging.debug("SetChannel2=%i" % channelbit)
self.channel2=channel
- self.channel3=0
+ self.channel3=-1
return self.i2csetget(self.SWaddr2,[channel])
def SetSW3(self,channelbit):
diff --git a/i2cserv/i2cp.py b/i2cserv/i2cp.py
new file mode 100644
index 0000000000000000000000000000000000000000..897d2e74538c68383728c61eeef2a206e55fdd92
--- /dev/null
+++ b/i2cserv/i2cp.py
@@ -0,0 +1,48 @@
+import os
+#if os.sys.platform is 'linux':
+#import pylibi2c;
+import time
+import logging
+#read=0: write to register
+#read=1: read from register
+#read=2: write to register (common in group)
+#read=3: wait ms second
+from .hwdev import hwdev;
+
+from periphery import I2C;
+
+class i2cp(hwdev):
+ def __init__(self,config):
+ hwdev.__init__(self,config);
+ self.I2Cdev='/dev/i2c-'+str(config['parameters'][0]);
+ self.i2c=I2C(self.I2Cdev)
+ logging.info("i2c driver on port "+str(self.I2Cdev))
+ self.I2Ccounter=0
+
+ def i2csetget(self,addr,data,reg=None,read=0):
+# logging.debug(str(("I2C",addr,reg,data,read)))
+# try:
+ if True:
+ if read==3:
+ time.sleep(data[0]/1000.)
+ return True
+ logging.debug(str(("I2C",addr,reg,data,read)))
+
+ if read==1:
+ if not(reg is None): self.i2c.transfer(addr,[I2C.Message([reg])])
+ msgs=[I2C.Message(data,read=True)]
+ self.i2c.transfer(addr,msgs)
+ data[:]=msgs[0].data
+ logging.debug(str(("I2C get",addr,reg,data,read)))
+ else:
+ if reg is None:
+ msgs=[I2C.Message(data)]
+ else:
+ msgs=[I2C.Message([reg]),I2C.Message(data)]
+ self.i2c.transfer(addr,msgs)
+ logging.debug(str(("I2C set",addr,reg,bytes(bytearray(data)),read)))
+ return True;
+# except:
+ else:
+ return False;
+
diff --git a/opcuaserv/smbus_float.py b/opcuaserv/smbus_float.py
new file mode 100644
index 0000000000000000000000000000000000000000..87bafce16c1290ede4a5a9bd3bd59cbb85bd07e3
--- /dev/null
+++ b/opcuaserv/smbus_float.py
@@ -0,0 +1,18 @@
+def smbus_2bytes_to_float(data):
+ expo = ((data & 0xf8)>>3)
+ if expo > 2**4:
+ expo = expo-2**5
+ mantisse = ((data & 0x7)<<8) + ((data & 0xff00) >> 8)
+ output = mantisse * 2**expo
+ return output
+
+def smbus_2bytes_to_float_exp12(data,expo=-12):
+ mantisse = ((data & 0xff)<<8) + ((data & 0xff00) >> 8)
+# print(data,mantisse,expo)
+ output = mantisse * 2**expo
+ return output
+
+def smbus_2bytes_to_float_exp13(data):
+ return smbus_2bytes_to_float_exp12(data,expo=-13)
+
+
diff --git a/opcuaserv/yamlreader.py b/opcuaserv/yamlreader.py
index e0c3873729830e1d99f4322c022398b43a012c06..6e0de63474b9cf6caa093dcb8f2440c2fbc05561 100644
--- a/opcuaserv/yamlreader.py
+++ b/opcuaserv/yamlreader.py
@@ -3,6 +3,7 @@ import struct
import time
from yamlconfig import *
import logging
+from .smbus_float import *
def bytes2int(bts):
x=0;
for b in bts:
@@ -31,7 +32,7 @@ class yamlreader(yamlconfig):
self.OPCset(self.statusid,[1],[])
def AddVars(self,AddVarR,AddVarW):
- self.monitorvar=AddVarW(self.yamlfile+"_monitor_rate_RW",60,None,None,None)
+ self.monitorvar=AddVarW(self.yamlfile+"_monitor_rate_RW",30,None,None,None)
for v in self.conf['variables']:
# print(v)
dim1=v.get('dim',1);
@@ -160,6 +161,7 @@ class yamlreader(yamlconfig):
v=self.conf['variables'][id1];
dtype=v.get('dtype','integer');
width=(v.get('width',8)-1)//8+1
+ endian=v.get('endian','>');
logging.debug(str(("OPCset",width,data)))
if dtype=="boolean":
data2=[d==1 for d in data];
@@ -168,13 +170,13 @@ class yamlreader(yamlconfig):
if width<=1:
data2=[d for d in data]
elif width==2:
- data2 = struct.unpack('>%sH' % (len(data)//2), data)
+ data2 = struct.unpack(endian+'%sH' % (len(data)//2), data)
elif width==3:
- data2 = [struct.unpack('>L' ,bytearray([0])+data[x*3:x*3+3])[0] for x in range(len(data)//3)]
+ data2 = [struct.unpack(endian+'L' ,bytearray([0])+data[x*3:x*3+3])[0] for x in range(len(data)//3)]
elif width==4:
- data2 = struct.unpack('>%sL' % (len(data)//4), data)
+ data2 = struct.unpack(endian+'%sL' % (len(data)//4), data)
elif width==8:
- data2 = struct.unpack('>%sQ' % (len(data)//8), data)
+ data2 = struct.unpack(endian+'%sQ' % (len(data)//8), data)
else:
logging.warn("OPCset"+v['name']+" unsupported width!"+str(width))
return;
@@ -186,8 +188,12 @@ class yamlreader(yamlconfig):
logging.warn("OPCset unsupported type");
return;
if dtype=="double":
- scale=float(v.get('scale',1.))
- data2=[(d*scale) for d in data2]
+ scale=v.get('scale',1.)
+ if scale in ["smbus_2bytes_to_float","smbus_2bytes_to_float_exp12","smbus_2bytes_to_float_exp13"]:
+ data2=[eval(scale)(d) for d in data2]
+ else:
+ scale=float(scale)
+ data2=[(d*scale) for d in data2]
var1=v.get('OPCR')
if not(var1): var1=v.get('OPCW')
if not(var1):
diff --git a/testUNB2.py b/testUNB2.py
index a6e3530a84a32db8644c76e8258a8f93bae81b75..c3d0a58df1875e3e3a1ede61aef063c89b83a136 100644
--- a/testUNB2.py
+++ b/testUNB2.py
@@ -35,21 +35,42 @@ var1=RCU_conf.getvarid('UNB2_EEPROM_Unique_ID');
N=2;
mask=[i<1 for i in range(N)];
print("mask=",mask);
-RCU_I2C.readvar(var1,mask);
-
+#RCU_I2C.readvar(var1,mask);
-var1=RCU_conf.getvarid('UNB2_DC_DC_48V_12V_VIN');
+points=["UNB2_POL_SWITCH_1V2_VOUT","UNB2_POL_SWITCH_1V2_TEMP"]
+#points=UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_SWITCH_PHY_TEMP]
N=2;
-mask=[i<2 for i in range(N)];
+mask=[i<1 for i in range(N)];
print("mask=",mask);
-RCU_I2C.readvar(var1,mask);
+for p in points:
+ var1=RCU_conf.getvarid(p);
+# RCU_I2C.readvar(var1,mask);
+
+N=8;
+mask=[i<4 for i in range(N)];
+print("mask=",mask);
+var1=RCU_conf.getvarid("UNB2_FPGA_POL_CORE_IOUT")
+#RCU_I2C.readvar(var1,mask);
+
-var1=RCU_conf.getvarid('UNB2_FPGA_QSFP_CAGE_LOS');
N=48;
-mask=[i<8 for i in range(N)];
+mask=[i<15 for i in range(N)];
+print("mask=",mask);
+var1=RCU_conf.getvarid("UNB2_FPGA_QSFP_CAGE_TEMP")
+#RCU_I2C.readvar(var1,mask);
+
+N=16;
+mask=[i<2 for i in range(N)];
print("mask=",mask);
+var1=RCU_conf.getvarid("UNB2_FPGA_DDR4_SLOT_PART_NUMBER")
RCU_I2C.readvar(var1,mask);
+#var1=RCU_conf.getvarid('UNB2_FPGA_QSFP_CAGE_LOS');
+#N=48;
+#mask=[i<8 for i in range(N)];
+#print("mask=",mask);
+#RCU_I2C.readvar(var1,mask);
+
#var1=RCU_conf.getmethodid('RCU_on');
#N=32;
#mask=[i<2 for i in range(N)];