diff --git a/pypcc/config/RECVTR_HB.yaml b/pypcc/config/RECVTR_HB.yaml
index d482bb17755a9bee28d642d4083f64a1cac784c5..acdfe6d810828e8660df52c70fd5037f1c0efbd0 100644
--- a/pypcc/config/RECVTR_HB.yaml
+++ b/pypcc/config/RECVTR_HB.yaml
@@ -770,6 +770,15 @@ methods:
      - IO3.CONF2: 0
      - IO1.CONF1: 0
 #     - IO1.CONF2: 0
+#ADC SPI bus reset 
+     -  IO3_GPIO2: 0x40 #CS low
+     -  IO3_GPIO1: 0x17 #CLK high
+     -  IO3_GPIO1: 0x15 #CLK low
+     -  IO3_GPIO1: 0x17 #CLK high
+     -  IO3_GPIO1: 0x15 #CLK low
+     -  IO3_GPIO2: 0x47 #CS high
+
+
      - IO4.CONF1: 0xC0 #pin 0x40, 0x80 not used
      - IO4.CONF2: 0xF8 
      - IO4.GPIO1: 0x2A #DAB switch states: 0x2A or 0x51
diff --git a/pypcc/config/RECVTR_LB.yaml b/pypcc/config/RECVTR_LB.yaml
index 49eba6678df3c1a9abbbc23e3801244eaf09bcb0..7ecd309d11b4efe000bdf2ee0e88c1683932b1a8 100644
--- a/pypcc/config/RECVTR_LB.yaml
+++ b/pypcc/config/RECVTR_LB.yaml
@@ -510,12 +510,13 @@ variables:
      driver: I2C_RCU
      devreg:  [ADC1.test,ADC2.test,ADC3.test]
      width: 8
-     rw:  ro
+     rw:  rw
      dtype: uint8
      dim: 96
      dim2: [3,32]
      debug: true
      read_parallel: true
+     mask: ANT_mask
 
 
    - name: RCU_ADC_sync
@@ -681,6 +682,15 @@ methods:
      - IO3.POL1: 0
      - IO3.CONF1: 0
      - IO3.CONF2: 0
+
+#ADC SPI bus reset 
+     -  IO3_GPIO2: 0x40 #CS low
+     -  IO3_GPIO1: 0x17 #CLK high
+     -  IO3_GPIO1: 0x15 #CLK low
+     -  IO3_GPIO1: 0x17 #CLK high
+     -  IO3_GPIO1: 0x15 #CLK low
+     -  IO3_GPIO2: 0x47 #CS high
+
 #     - RCU_GPIO1: Update
 #     - RCU_GPIO2: Update
 #     - RCU_attenuator: [10,10,10]  #Set OPC-UA variable
diff --git a/python_scripts/ADCtest.py b/python_scripts/ADCtest.py
index b7003308807c0637a29164047e0652d8140e59b1..4277930277c95d9540c90097247a03aa2d86c38c 100644
--- a/python_scripts/ADCtest.py
+++ b/python_scripts/ADCtest.py
@@ -75,17 +75,37 @@ def SetReg(name,data,drvvar):
 #reading the ID also set the switch
 print("Get IDs")
 data,var1=GetVal(varID);
+print(data)
 data=np.array(data)[::4]
 mask=[not(d is None) for d in data]
-#print(data)
 print(mask)
 #GetReg("GPIO3.
 #SetReg("IO3.GPIO1",[21]*32)
 #SetReg("IO3.GPIO2",[71]*32)
+
+#exit()
+data,var1=GetVal("RCU_IO1_GPIO1")
+data,var1=GetVal("RCU_IO1_GPIO2")
+data,var1=GetVal("RCU_IO2_GPIO1")
+data,var1=GetVal("RCU_IO2_GPIO2")
+
+if False:
+  SetVal("RCU_IO3_GPIO1",[0]*32)
+  SetVal("RCU_IO3_GPIO2",[0]*32)
+  SetVal("RCU_PWR_DIGITAL_on",[0]*32)
+  SetVal("RCU_PWR_DIGITAL_on",[1]*32)
+
 SetVal("RCU_IO3_GPIO1",[21]*32)
 SetVal("RCU_IO3_GPIO2",[71]*32)
+SetReg("IO3.CONF1",[0]*32,"RCU_IO3_GPIO1")
+SetReg("IO3.CONF2",[0]*32,"RCU_IO3_GPIO1")
+SetReg("IO3.POL1",[0]*32,"RCU_IO3_GPIO1")
+SetReg("IO3.POL2",[0]*32,"RCU_IO3_GPIO1")
+
+
+data,var1=GetVal("RCU_PWR_DIGITAL_on")
+print("RCU_PWR_DIGITAL_on",data)
 
-#exit()
 data,var1=GetVal("RCU_IO3_GPIO1")
 print("RCU_IO3_GPIO1",data)
 data,var1=GetVal("RCU_IO3_GPIO2")
@@ -94,15 +114,39 @@ print("RCU_IO3_GPIO2",data)
 #exit()
 #print("Read Reg")
 
-#data,var1=GetVal(regname);
-#data=np.array(data).reshape([32,3])
-#print(data)
+if False:
+  SetVal("RCU_ADC_shutdown",[1]*96)
+  SetVal("RCU_ADC_shutdown",[0]*96)
+data,var1=GetVal("RCU_ADC_shutdown")
+print("RCU_ADC_shutdown",data)
+
+if True: #SPI bus reset
+  SetVal("RCU_IO3_GPIO2",[0x40]*32) #bit0,1,2 = CS = Low
+  SetVal("RCU_IO3_GPIO1",[0x17]*32) #CLK high 
+  SetVal("RCU_IO3_GPIO1",[0x15]*32) #CLK low
+  SetVal("RCU_IO3_GPIO1",[0x17]*32) #CLK high
+  SetVal("RCU_IO3_GPIO1",[0x15]*32) #CLK low
+  SetVal("RCU_IO3_GPIO2",[0x47]*32) #CS = High
+#  for x in range(1):
+#     SetVal("RCU_IO3_GPIO1",[0x02]*32) #CLK high
+#     SetVal("RCU_IO3_GPIO1",[0x00]*32) #CLK low
+
+#  SetVal("RCU_IO3_GPIO1",[0x15]*32) #CLK low
+  time.sleep(1)
+
+SetReg("ADC2.test",[2]*32,regname)
+SetReg("ADC3.test",[3]*32,regname)
+SetReg("ADC1.test",[1]*32,regname)
+
+data,var1=GetVal(regname);
+data=np.array(data).reshape([32,3])
+print(data)
 #exit()
 for x in range(1,100):
   print("Set reg",x)
-  SetReg("ADC1.test",[x]*32,regname)
-  SetReg("ADC2.test",[x+1]*32,regname)
   SetReg("ADC3.test",[x+2]*32,regname)
+  SetReg("ADC2.test",[x+1]*32,regname)
+  SetReg("ADC1.test",[x]*32,regname)
 #  data=np.array([x]*96)
 #  SetVal(regname,data)