diff --git a/pypcc/config/RECVTR_HB.yaml b/pypcc/config/RECVTR_HB.yaml
index 771758293b7396f53cbbdd956c433be3886c2f48..787c2bef358f5fed6b089b06d5e7cc8fe6b9285c 100644
--- a/pypcc/config/RECVTR_HB.yaml
+++ b/pypcc/config/RECVTR_HB.yaml
@@ -191,6 +191,9 @@ device_registers:
- name: JESD_control1
description: JESD link control
address: 0x5F
+ - name: JESD_control3
+ description: JESD link control
+ address: 0x61
- name: SYNC_control
address: 0x3A
- name: CML_level
@@ -572,6 +575,29 @@ variables:
dim: 96
dim2: [3,32]
debug: true
+ mask: ANT_mask
+
+ - name: RCU_ADC_testsignal
+ driver: I2C_RCU
+ devreg: [ADC1.JESD_control1,ADC2.JESD_control1,ADC3.JESD_control1]
+ width: 1
+ bitoffset: 5
+ rw: ro
+ dtype: boolean
+ dim: 96
+ dim2: [3,32]
+ mask: ANT_mask
+
+ - name: RCU_ADC_JESD3
+ driver: I2C_RCU
+ devreg: [ADC1.JESD_control3,ADC2.JESD_control3,ADC3.JESD_control3]
+ width: 8
+ rw: rw
+ dtype: uint8
+ dim: 96
+ dim2: [3,32]
+ debug: true
+ mask: ANT_mask
- name: RCU_ADC_CML_level
driver: I2C_RCU
@@ -745,6 +771,7 @@ methods:
- RCU_update: 0
- RCU_ADC_locked: Update #check if not also in RCU_update
- RCU_ADC_sync: Update #disabled for testing
+ - RCU_ADC_testsignal: Update #disabled for testing
- RCU_DTH_on: Update #check if not also in RCU_update
- RCU_IO4_GPIO1: Update #should be last, as it will fail for low-band
- RCU_IO4_GPIO2: Update
@@ -789,7 +816,7 @@ methods:
- IO1.CONF1: 0
# - IO1.CONF2: 0
#ADC SPI bus reset
- - IO3.GPIO2: 0x40 #CS low
+ - IO3.GPIO2: 0xC0 #CS low, DTH Shutdown
- IO3.GPIO1: 0x17 #CLK high
- IO3.GPIO1: 0x15 #CLK low
- IO3.GPIO1: 0x17 #CLK high
@@ -828,6 +855,7 @@ methods:
- RCU_DTH_on: Update #check dither while giving ADCs some time to lock
- RCU_ADC_locked: Update #disabled for testing
- RCU_ADC_sync: Update #disabled for testing
+ - RCU_ADC_testsignal: Update #disabled for testing
- name: RCU_update
@@ -971,3 +999,14 @@ methods:
- DTH2.Start : [0,1,0,0,1]
- DTH3.Start : [0,1,0,0,1]
+
+ - name: RCU_ADC_testsignal_on
+ driver: I2C_RCU
+ instructions:
+ - ADC1.JESD_control1 : 0x34
+ - ADC1.Update: 1 #Needed to update ADC registers
+ - ADC2.JESD_control1 : 0x34
+ - ADC2.Update: 1 #Needed to update ADC registers
+ - ADC3.JESD_control1 : 0x34
+ - ADC3.Update: 1 #Needed to update ADC registers
+ - RCU_ADC_testsignal: Update #disabled for testing
diff --git a/pypcc/config/RECVTR_LB.yaml b/pypcc/config/RECVTR_LB.yaml
index ac308f198ae090e3456cabed75158f07fe50adf7..62c10a62392de11b597826f01b9bedb1b5ac79a8 100644
--- a/pypcc/config/RECVTR_LB.yaml
+++ b/pypcc/config/RECVTR_LB.yaml
@@ -141,7 +141,6 @@ device_registers:
- name: JESD_control1
description: JESD link control
address: 0x5F
- store: True
- name: JESD_control3
description: JESD link control
address: 0x61
@@ -550,7 +549,7 @@ variables:
devreg: [ADC1.JESD_control1,ADC2.JESD_control1,ADC3.JESD_control1]
width: 1
bitoffset: 5
- rw: rw
+ rw: ro
dtype: boolean
dim: 96
dim2: [3,32]
@@ -699,8 +698,8 @@ methods:
#Set registers to default values
- IO2.GPIO1: 0x4A #0x40 Dig on, 0x0a =10dB att
- IO2.GPIO2: 0x55 #0x15 #Band0 (or 0x2a band 1) #LED green=on=low
- - IO3.GPIO1: 0x95 #0001 0101 ADC_SDIO=high, clk=low, DTH_shutdown=HIGH (made low which ADC SPI bus reset)
- - IO3.GPIO2: 0x47 #ADC SC=high, DTH_SDA=high, DTH_EN=low
+ - IO3.GPIO1: 0x15 #0001 0101 ADC_SDIO=high, clk=low, DTH_en=low
+ - IO3.GPIO2: 0x47 #ADC SC=high, DTH_SDA=high, DTH_SDA=low
- IO1.GPIO1: 0x0A #0x0a = 10dB att
# - IO1.POL1: 0
# - IO1.POL2: 0
@@ -714,7 +713,7 @@ methods:
- IO3.CONF2: 0
#ADC SPI bus reset
- - IO3.GPIO2: 0x40 #CS low
+ - IO3.GPIO2: 0xC0 #CS low, DTH shutdown
- IO3.GPIO1: 0x17 #CLK high
- IO3.GPIO1: 0x15 #CLK low
- IO3.GPIO1: 0x17 #CLK high
@@ -882,3 +881,13 @@ methods:
- DTH2.Start : [0,1,0,0,1]
- DTH3.Start : [0,1,0,0,1]
+ - name: RCU_ADC_testsignal_on
+ driver: I2C_RCU
+ instructions:
+ - ADC1.JESD_control1 : 0x34
+ - ADC1.Update: 1 #Needed to update ADC registers
+ - ADC2.JESD_control1 : 0x34
+ - ADC2.Update: 1 #Needed to update ADC registers
+ - ADC3.JESD_control1 : 0x34
+ - ADC3.Update: 1 #Needed to update ADC registers
+ - RCU_ADC_testsignal: Update #disabled for testing
diff --git a/scripts/ADC_JESDtest.py b/scripts/ADC_JESDtest.py
index 1bf67939f50aaafcb7a0559e536aeb3864945715..1703d280dd14940d311f1ac6eae329b86d50d1f3 100644
--- a/scripts/ADC_JESDtest.py
+++ b/scripts/ADC_JESDtest.py
@@ -2,11 +2,11 @@ from test_common import *
connect()
#name="RCU_ADC_JESD3"
-name="RCU_ADC_JESD"
+name="RCU_ADC_testsignal"
#RCU=[0];
RCU=[x for x in range(32)];
-Att=[0x14]*3 #default
-Att=[0x34]*3
+Att=[False]*3 #default
+Att=[True]*3
#RCU=[0,1,2,3,16,17,18,19];
#Att=[0x24]*3 #8-bit 0010, 0100 PN9
#Att=[10,10,10]
@@ -14,15 +14,21 @@ Att=[0x34]*3
setAntmask(RCU)
-att=get_debug_value(name+"_R")
+wait_not_busy("RECVTR_translator_busy_R",10)
+att=get_value(name+"_R")
print("JESD old:",att[:15])
-for r in RCU:
- att[3*r:3*r+3]=Att
-print("JESD set:",att[:15])
-set_debug_value(name+"_RW",att)
-time.sleep(0.5)
-att=get_debug_value(name+"_R")
-print("JESD new:",att[:15])
+#for r in RCU:
+# att[3*r:3*r+3]=Att
+#print("JESD set:",att[:15])
+#set_value(name+"_RW",att)
+if True:
+ callmethod("RCU_ADC_testsignal_on")
+
+ time.sleep(0.5)
+ wait_not_busy("RECVTR_translator_busy_R",10)
+ att=get_value(name+"_R")
+
+ print("JESD new:",att[:15])
disconnect()
\ No newline at end of file