From c13349a514b6ab08584a7dfa59766ef7d0229c50 Mon Sep 17 00:00:00 2001
From: Paulus <kruger@astron.nl>
Date: Tue, 23 Feb 2021 11:40:03 +0000
Subject: [PATCH] Clock board added
---
clk/HWconf.py | 2 +-
clk/Vars.py | 26 ++++++++++++++++----------
clk/spibitbang2.py | 19 ++++++++++++-------
i2c/I2C.py | 12 ++++++++----
i2c/I2C_dummy.py | 4 ++--
i2c/setswitch.py | 34 ++++++++++++++++++++++++++++++++++
pcctypes.py | 1 +
pypcc2.py | 6 +++---
rcu/HWconf.py | 11 +++++++----
rcu/RCU.py | 21 +++++++++++++++++----
rcu/Vars.py | 30 +++++++++++++++++++-----------
rcu/spibitbang1.py | 10 ++++++----
scripts/ADCreset.py | 9 +++++----
scripts/CLK.py | 16 ++++++++++++++++
scripts/RCUupdate.py | 4 +++-
scripts/SetHBAT_BF.py | 26 ++++++++++++++++++++++++++
scripts/SetHBAT_LED.py | 28 ++++++++++++++++++++++++++++
scripts/SetHBA_BF.py | 4 ++--
scripts/SetHBA_LED.py | 6 +++---
scripts/test_common.py | 7 ++++---
20 files changed, 213 insertions(+), 63 deletions(-)
create mode 100644 i2c/setswitch.py
create mode 100644 scripts/CLK.py
create mode 100644 scripts/SetHBAT_BF.py
create mode 100644 scripts/SetHBAT_LED.py
diff --git a/clk/HWconf.py b/clk/HWconf.py
index 36f1437..b975665 100644
--- a/clk/HWconf.py
+++ b/clk/HWconf.py
@@ -14,6 +14,6 @@ RCU_storeReg=4; #Number of stored registers
-SPIBB_PLL=BBdev(4,[CLK_IO3_OUT1,CLK_IO3_OUT1,CLK_IO3_OUT1,CLK_IO3_OUT2],[4,7,5,6],0) #CLK,SDI,SDO,CS
+SPIBB_PLL=BBdev(4,[CLK_IO3_OUT1,CLK_IO3_OUT1,CLK_IO3_OUT1,CLK_IO3_OUT1],[4,7,5,6],0) #CLK,SDI,SDO,CS
CLK_PLL_lock =DevReg(SPIBB_PLL,0X00,0X00,0) # PLL locked status
diff --git a/clk/Vars.py b/clk/Vars.py
index 20c67ab..7e49e3a 100644
--- a/clk/Vars.py
+++ b/clk/Vars.py
@@ -3,33 +3,38 @@ from .HWconf import *
CLKmod=I2Cmodules.CLK
-CLK_IGNORE_PPS= VarArray("CLK_Ignore_PPS",1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,1 ,6,1)],RW.ReadOnly,datatype.dInt,1,None,None)
-CLK_Enable_PWR= VarArray("CLK_Enable_PWR",1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,1 ,7,1)],RW.ReadOnly,datatype.dInt,1,None,None)
-CLK_Stat1 = VarArray("CLK_Stat" ,1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,1 ,4,1)],RW.ReadOnly,datatype.dInt,1,None,None)
+CLK_IGNORE_PPS= VarArray("CLK_Ignore_PPS",1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT2,1 ,2,1)],RW.ReadOnly,datatype.dInt,1,None,None)
+CLK_Enable_PWR= VarArray("CLK_Enable_PWR",1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,1 ,1,1)],RW.ReadOnly,datatype.dInt,1,None,None)
+CLK_Stat1 = VarArray("CLK_Stat" ,1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,1 ,2,1)],RW.ReadOnly,datatype.dInt,1,None,None)
CLK_lock1 = VarArray("CLK_Lock" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_lock,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None)
-OPC_devvars=[CLK_IGNORE_PPS,CLK_Enable_PWR,CLK_Stat1,CLK_lock1]
+OPC_devvars=[CLK_Enable_PWR,CLK_lock1]
RCU_init=Instrs("ReadRegisters",2,[
Instr(DevType.VarUpdate,CLK_IGNORE_PPS,1,[0]),
Instr(DevType.VarUpdate,CLK_Enable_PWR,1,[0])
])
-CLK_on=Instrs("CLK_on",2,[
+CLK_on=Instrs("CLK_on",3,[
Instr(DevType.I2C,CLK_IO3_CONF1,1,[0x2C]),
Instr(DevType.I2C,CLK_IO3_OUT1 ,1,[0x42]),
+ Instr(DevType.VarUpdate,CLK_lock1,1,[0]),
+ Instr(DevType.VarUpdate,CLK_Enable_PWR,1,[0])
])
-CLK_off=Instrs("CLK_off",2,[
+CLK_off=Instrs("CLK_off",3,[
Instr(DevType.I2C,CLK_IO3_CONF1,1,[0x2C]),
Instr(DevType.I2C,CLK_IO3_OUT1 ,1,[0x40]),
+ Instr(DevType.VarUpdate,CLK_Enable_PWR,1,[0])
])
def SPIinst(reg,value):
- return Instr(DevType.SPIbb,DevReg(SPIBB_PLL,0,reg,0),1,[value]),
-CLK_PLL_setup=Instrs("CLK_PLL_setup",2,[
- SPIinst(0x03,0x08),
+ return Instr(DevType.SPIbb,DevReg(SPIBB_PLL,0,reg,0),1,[value])
+
+CLK_PLL_setup=Instrs("CLK_PLL_setup",15,[
+# SPIinst(0x03,0x08),
+# Instr(DevType.I2C,CLK_IO3_CONF1,1,[0x2C]),
SPIinst(0x05,0x97),
SPIinst(0x06,0x10),
SPIinst(0x07,0x04),
@@ -41,7 +46,8 @@ CLK_PLL_setup=Instrs("CLK_PLL_setup",2,[
SPIinst(0x0D,0x01),#was 2
SPIinst(0x0F,0x01),
SPIinst(0x11,0x01),
- SPIinst(0x13,0x01)
+ SPIinst(0x13,0x01),
+ Instr(DevType.VarUpdate,CLK_lock1,1,[0])
])
OPC_methods=[CLK_on,CLK_off,CLK_PLL_setup]
diff --git a/clk/spibitbang2.py b/clk/spibitbang2.py
index d7d6be0..f51d9a2 100644
--- a/clk/spibitbang2.py
+++ b/clk/spibitbang2.py
@@ -19,19 +19,22 @@ def SetSPIbb(SetI2C,RCUi,dev,value):
CLKdev=dev.Addr.devs[SPIBB_pins.CLK.value]
CLKpin=dev.Addr.pins[SPIBB_pins.CLK.value]
- logging.info(str(("SPIbb set",ADC_address,value)))
-
+ logging.warn(str(("SPIbb set",ADC_address,value)))
+
# dev_rw = 0x00 # 0 for write, 1 for read
# data2 = ( reg_address << 9 ) + ( dev_rw << 8 ) + value[0]
data2 = ( ADC_address << 9 ) + value[0]
bit_array = "{0:{fill}16b}".format(data2, fill='0')
# print(bit_array)
+ SetI2C(RCUi,CSdev,1,CSpin,[1]) #disable
SetI2C(RCUi,CSdev,1,CSpin,[0]) #enable
for bit in bit_array:
+ SetI2C(RCUi,CLKdev,1,CLKpin,[0])
SetI2C(RCUi,SDIdev,1,SDIpin,[int(bit)])
SetI2C(RCUi,CLKdev,1,CLKpin,[1])
- SetI2C(RCUi,CLKdev,1,CLKpin,[0])
+ SetI2C(RCUi,CLKdev,1,CLKpin,[0])#Why?
+ SetI2C(RCUi,CLKdev,1,CLKpin,[1])
SetI2C(RCUi,CSdev,1,CSpin,[1]) #disable
# SetI2C(RCUi,SDIdev,1,SDIpin,[1]) #high when finished
return True;
@@ -47,19 +50,20 @@ def GetSPIbb(SetI2C,GetI2C,RCUi,dev,value):
CLKdev=dev.Addr.devs[SPIBB_pins.CLK.value]
CLKpin=dev.Addr.pins[SPIBB_pins.CLK.value]
- logging.info(str(("SPIbb get",ADC_reg_address)))
+ logging.warn(str(("SPIbb get",ADC_reg_address)))
ADC_bytes = 0x00
# ADC_rw = 0x01 # 0 for write, 1 for read
data = (ADC_reg_address << 1) + 1 #was 7??
+ SetI2C(RCUi,CSdev,1,CSpin,[1]) #disable
SetI2C(RCUi,CSdev,1,CSpin,[0]) #enable
bit_array = "{0:{fill}8b}".format(data, fill='0')
for bit in bit_array:
SetI2C(RCUi,SDIdev,1,SDIpin,[int(bit)])
- SetI2C(RCUi,CLKdev,1,CLKpin,[1])
SetI2C(RCUi,CLKdev,1,CLKpin,[0])
+ SetI2C(RCUi,CLKdev,1,CLKpin,[1])
# SetI2C(RCUi,SDIdev,1,SDIpin,[1]) #high when finished
@@ -69,10 +73,11 @@ def GetSPIbb(SetI2C,GetI2C,RCUi,dev,value):
ret_value=[0]
for i in range(N): value[i]=0
for cnt in range(8*(ADC_bytes+1)):
+ SetI2C(RCUi,CLKdev,1,CLKpin,[0])
+ SetI2C(RCUi,CLKdev,1,CLKpin,[1]) #read after rising
GetI2C(RCUi,SDOdev,1,SDOpin,ret_value)
for i in range(N): value[i]=(value[i]<<1)+ ret_value[i]
- SetI2C(RCUi,CLKdev,1,CLKpin,[1])
- SetI2C(RCUi,CLKdev,1,CLKpin,[0]) #read after falling edge
+ SetI2C(RCUi,CLKdev,1,CLKpin,[0])
SetI2C(RCUi,CSdev,1,CSpin,[1]) #disable
return True;
diff --git a/i2c/I2C.py b/i2c/I2C.py
index 7d5b619..1982b43 100644
--- a/i2c/I2C.py
+++ b/i2c/I2C.py
@@ -9,21 +9,22 @@ import logging
I2Ccounter=0;
def I2C1server(addr,data,reg=None,read=0):
+# print("I2C",addr,reg,data,read)
try:
if read==3:
time.sleep(data[0]/1000.)
return True
logging.debug(str(("I2C",addr,reg,data,read)))
-# print("I2C",addr,reg,data,read)
# return True;
- bus=pylibi2c.I2CDevice('/dev/i2c-2',addr)
+ bus=pylibi2c.I2CDevice('/dev/i2c-1',addr)
if read==1:
length=len(data)
bus.iaddr_bytes=0
if not(reg is None):
bus.ioctl_write(0,str(bytearray([reg])))
data[:]=[int(x) for x in bus.ioctl_read(0,length)]
+# print("I2C read",addr,reg,data,read)
else:
if reg is None:
bus.iaddr_bytes=0
@@ -36,7 +37,8 @@ def I2C1server(addr,data,reg=None,read=0):
# data[0]=0xff
return False;
-def I2C2server(addr,data,reg=None,read=0):
+def I2C4server(addr,data,reg=None,read=0):
+# print("I2C4",addr,reg,data,read)
try:
if read==3:
time.sleep(data[0]/1000.)
@@ -45,13 +47,14 @@ def I2C2server(addr,data,reg=None,read=0):
# print("I2C",addr,reg,data,read)
# return True;
- bus=pylibi2c.I2CDevice('/dev/i2c-1',addr)
+ bus=pylibi2c.I2CDevice('/dev/i2c-4',addr)
if read==1:
length=len(data)
bus.iaddr_bytes=0
if not(reg is None):
bus.ioctl_write(0,str(bytearray([reg])))
data[:]=[int(x) for x in bus.ioctl_read(0,length)]
+# print(data)
else:
if reg is None:
bus.iaddr_bytes=0
@@ -61,6 +64,7 @@ def I2C2server(addr,data,reg=None,read=0):
return True;
except:
if bus: bus.close()
+ print("I2C4 error")
# data[0]=0xff
return False;
diff --git a/i2c/I2C_dummy.py b/i2c/I2C_dummy.py
index d6351b0..ba39c1a 100644
--- a/i2c/I2C_dummy.py
+++ b/i2c/I2C_dummy.py
@@ -20,9 +20,9 @@ def I2C1server(addr,data,reg=None,read=0):
# logging.debug(str(("I2C",addr,reg,data,read)))
return True
-def I2C2server(addr,data,reg=None,read=0):
+def I2C4server(addr,data,reg=None,read=0):
global I2Ccounter;
- logging.debug(str(("I2C2",addr,reg,data,read)))
+ logging.debug(str(("I2C4",addr,reg,data,read)))
if read==3:
time.sleep(data[0]/1000.)
return True
diff --git a/i2c/setswitch.py b/i2c/setswitch.py
new file mode 100644
index 0000000..8871663
--- /dev/null
+++ b/i2c/setswitch.py
@@ -0,0 +1,34 @@
+from I2C import *
+import time
+RCU=2
+Ver="RCU2H v0.2"
+R1=0
+ROM=0x50
+
+#Set switch
+print("Set switch")
+if not(I2C1server(0x70,[1<<RCU],reg=None,read=0)): exit() #select RCU
+exit()
+#Get ID
+print("Get ID")
+ID=[0]*4
+if not(I2C1server(ROM,ID,reg=0xFC,read=1)): exit() #select RCU
+print(ID)
+exit()
+
+#Upload version
+Ver2=[(c.encode('utf-8')[0]) for c in Ver]
+print(len(Ver),Ver,Ver2)
+V2=[0]
+for i,v in enumerate(Ver2):
+ time.sleep(0.1)
+ I2C1server(ROM,[v],reg=R1+i,read=0) #select RCU
+# I2C1server(ROM,[v],reg=None,read=0) #select RCU
+ time.sleep(0.1)
+ I2C1server(ROM,V2,reg=R1+i,read=1) #select RCU
+ print(i,v,V2)
+
+#Download version
+Ver2=[0]*10
+I2C1server(ROM,Ver2,reg=R1,read=1) #select RCU
+print(Ver2)
diff --git a/pcctypes.py b/pcctypes.py
index e25c0b7..56c4bc7 100644
--- a/pcctypes.py
+++ b/pcctypes.py
@@ -35,6 +35,7 @@ class DevType(Enum):
Internal = 6
HBA1 = 7
HBA2 = 8
+ Wait = 9
class RW(Enum):
Hidden = 0 #Not an OPC_UA variable
diff --git a/pypcc2.py b/pypcc2.py
index 6ba9f38..79dd46a 100644
--- a/pypcc2.py
+++ b/pypcc2.py
@@ -43,14 +43,14 @@ opcuaserv.InitServer(port=args.port)
logging.info("OPC-UA Server started")
SW1=I2Cswitch1.I2Cswitch1(I2C.I2C1server)
-SW0=I2Cswitch1.I2Cswitch0(I2C.I2C2server) #Dummy switch as their is no switch on LTS
+SW0=I2Cswitch1.I2Cswitch0(None) #Dummy switch as their is no switch on LTS
RCU=RCU.RCU1(NRCU,I2C.I2C1server,SW1.SetChannel)
RCU.AddVars(Q1,opcuaserv.AddVarR,opcuaserv.AddVarW)
RCU.AddMethod(Q1,opcuaserv.Addmethod)
RCU.load() #Load current register values from HW
-CLK=CLK.RCU1(1,I2C.I2C2server,SW0.SetChannel)
+CLK=CLK.RCU1(1,I2C.I2C4server,SW0.SetChannel)
CLK.AddVars(Q2,opcuaserv.AddVarR,opcuaserv.AddVarW)
CLK.AddMethod(Q2,opcuaserv.Addmethod)
CLK.load() #Load current register values from HW
@@ -106,5 +106,5 @@ finally:
logging.info("Stop OPC-UA server")
opcuaserv.server.stop()
RCUthread1.join()
-# CLKthread1.join()
+ CLKthread1.join()
Timerthread1.join()
diff --git a/rcu/HWconf.py b/rcu/HWconf.py
index 38fa659..44b75df 100644
--- a/rcu/HWconf.py
+++ b/rcu/HWconf.py
@@ -27,10 +27,10 @@ RCU_IO2_OUT2=DevReg(0x76,1,3,6)
RCU_IO2_CONF1=DevReg(0x76,6,6,7)
RCU_IO2_CONF2=DevReg(0x76,7,7,8)
#Device: TCA6416
-RCU_IO3_OUT1=DevReg(0x2F,0,2,9)
-RCU_IO3_OUT2=DevReg(0x2F,1,3,10)
-RCU_IO3_CONF1=DevReg(0x2F,6,6,11)
-RCU_IO3_CONF2=DevReg(0x2F,7,7,12)
+RCU_IO3_OUT1=DevReg(0x20,0,2,9)
+RCU_IO3_OUT2=DevReg(0x20,1,3,10)
+RCU_IO3_CONF1=DevReg(0x20,6,6,11)
+RCU_IO3_CONF2=DevReg(0x20,7,7,12)
RCU_storeReg=13; #Number of stored registers
@@ -63,18 +63,21 @@ SPIBB_ADC3=BBdev(4,[RCU_IO3_OUT1,RCU_IO3_OUT1,RCU_IO3_CONF1,RCU_IO3_OUT2],[5,4,4
#SPI ADC
#Dev: AD9683
RCU_ADC1_PLL_stat =DevReg(SPIBB_ADC1,0X0A,0X0A,0) # PLL locked status
+RCU_ADC1_PLL_enc =DevReg(SPIBB_ADC1,0X21,0X21,0) # PLL low encode
RCU_ADC1_JESD_ctr =DevReg(SPIBB_ADC1,0X5F,0X5F,0) #JESD link control, ILAS mode
RCU_ADC1_CML_level=DevReg(SPIBB_ADC1,0X15,0X15,0) #CML output adjust
RCU_ADC1_SYNC_ctr =DevReg(SPIBB_ADC1,0X3A,0X3A,0) #SYNC / SYSREF control
RCU_ADC1_update =DevReg(SPIBB_ADC1,0XFF,0xFF,0) # Global device update
RCU_ADC2_PLL_stat =DevReg(SPIBB_ADC2,0X0A,0X0A,0) # PLL locked status
+RCU_ADC2_PLL_enc =DevReg(SPIBB_ADC2,0X21,0X21,0) # PLL low encode
RCU_ADC2_JESD_ctr =DevReg(SPIBB_ADC2,0X5F,0X5F,0) #JESD link control, ILAS mode
RCU_ADC2_CML_level=DevReg(SPIBB_ADC2,0X15,0X15,0) #CML output adjust
RCU_ADC2_SYNC_ctr =DevReg(SPIBB_ADC2,0X3A,0X3A,0) #SYNC / SYSREF control
RCU_ADC2_update =DevReg(SPIBB_ADC2,0XFF,0xFF,0) # Global device update
RCU_ADC3_PLL_stat =DevReg(SPIBB_ADC3,0X0A,0X0A,0) # PLL locked status
+RCU_ADC3_PLL_enc =DevReg(SPIBB_ADC3,0X21,0X21,0) # PLL low encode
RCU_ADC3_JESD_ctr =DevReg(SPIBB_ADC3,0X5F,0X5F,0) #JESD link control, ILAS mode
RCU_ADC3_CML_level=DevReg(SPIBB_ADC3,0X15,0X15,0) #CML output adjust
RCU_ADC3_SYNC_ctr =DevReg(SPIBB_ADC3,0X3A,0X3A,0) #SYNC / SYSREF control
diff --git a/rcu/RCU.py b/rcu/RCU.py
index 6f9fc17..9b8d41c 100644
--- a/rcu/RCU.py
+++ b/rcu/RCU.py
@@ -3,6 +3,7 @@ import numpy as np
import logging
from .spibitbang1 import *
import threading
+import time
def ApplyMask(value,width=8,bitoffset=0,previous=0):
@@ -77,6 +78,10 @@ class RCU1():
def SetVar(self,Instr,Mask=[]):
# Instr.value=strs2bytes(Instr.value) #Alwast be an array of bytes
+ if Instr.type==Vars.DevType.Wait:
+# time.sleep(Instr.value[0]/1000.)
+ print("Sleep",Instr.value[0]/1000.,"s")
+ return;
if Instr.type==Vars.DevType.Instr:
#Execute instructions
Iset=Instr.dev;
@@ -108,6 +113,7 @@ class RCU1():
# self.SetI2C(RCUi,Instr.dev,8,0,strs2bytes(Instr.value))
return;
V1=Instr.dev
+# print(Instr.nvalue,V1.nVars,V1.size)
if not((Instr.nvalue==V1.nVars) and (Instr.type==Vars.DevType.VarUpdate)) and not(Instr.nvalue==V1.size*self.N):
logging.error("Wrong size of value")
return False
@@ -187,6 +193,8 @@ class RCU1():
elif V1.Vars[0].type==Vars.DevType.HBA1:
for Vari in range(Step):
var=V1.Vars[Vari]
+# self.SWcallback(mask)
+# self.SetI2CAddr(self,DevReg)
for RCUi in range(self.N):
self.SWcallback(1<<Vars.RCU_MPaddr.Switch[RCUi])
# print(Step,Step2,len(value1),V1.size)
@@ -263,9 +271,14 @@ class RCU1():
value[i]=ApplyMask(value[i],width,bitoffset,previous[i]);
self.previousHBA[RCUi,dev.store-1]=value
# if buffer: return True;
+ XX=[0]
+ self.I2Ccallback(0x40,XX,reg=0,read=1)#wakeup, do nothing
+ self.I2Ccallback(dev.Addr,[10],read=3)
self.I2Ccallback(dev.Addr,value[:16],reg=dev.Register_W)
- if L>16: self.I2Ccallback(dev.Addr,value[16:],reg=dev.Register_W+16)
- self.I2Ccallback(dev.Addr,[500],reg=dev.Register_W,read=3) #Wait 500ms
+ if L>16:
+ self.I2Ccallback(dev.Addr,[10],read=3)
+ self.I2Ccallback(dev.Addr,value[16:],reg=dev.Register_W+16)
+ self.I2Ccallback(dev.Addr,[600],reg=dev.Register_W,read=3) #Wait 500ms
return True
# return self.I2Ccallback(dev.Addr,value,reg=dev.Register_W)
@@ -370,8 +383,8 @@ class RCU1():
def Queue_Monitor(self,Q1,NRCU):
Inst1=Vars.Instr(Vars.DevType.VarUpdate,Vars.RCU_temp,NRCU,[0]*NRCU)
Q1.put(Inst1)
-# Inst1=Vars.Instr(Vars.DevType.VarUpdate,Vars.RCU_ADC_lock,96,[0]*96)
-# Q1.put(Inst1)
+ Inst1=Vars.Instr(Vars.DevType.VarUpdate,Vars.RCU_ADC_lock,96,[0]*96)
+ Q1.put(Inst1)
return
def AddVars(self,Q1,AddVarR,AddVarW):
for v in Vars.OPC_devvars:
diff --git a/rcu/Vars.py b/rcu/Vars.py
index 5617ec0..8857161 100644
--- a/rcu/Vars.py
+++ b/rcu/Vars.py
@@ -103,7 +103,9 @@ RCU_OUT2=VarArray("RCU_OUT2",3,[RCU_IO1_2,RCU_IO2_2,RCU_IO3_2],RW.ReadOnly,datat
#RCU_CNF1=VarArray("RCU_CONF1",3,[RCU_IO1_3,RCU_IO2_3,RCU_IO3_3],RW.ReadOnly,datatype.dInt,None,None)
#RCU_CNF2=VarArray("RCU_CONF2",3,[RCU_IO1_4,RCU_IO2_4,RCU_IO3_4],RW.ReadOnly,datatype.dInt,None,None)
-OPC_devvars=[RCU_mask,Ant_mask,RCU_att,RCU_band,RCU_temp,RCU_pwrd,RCU_LED,RCU_ADC_lock,RCU_ADC_SYNC,RCU_ADC_JESD,RCU_ADC_CML,RCU_OUT1,RCU_OUT2,RCU_ID,RCU_VER,HBA_Delay,HBA_led]
+#OPC_devvars=[RCU_mask,Ant_mask,RCU_att,RCU_band,RCU_temp,RCU_pwrd,RCU_LED,RCU_ID,RCU_VER,HBA_Delay,HBA_led]
+#OPC_devvars=[RCU_mask,Ant_mask,RCU_att,RCU_band,RCU_temp,RCU_pwrd,RCU_LED,RCU_ID,RCU_VER,HBA_Delay,HBA_led,RCU_uCV_ID]
+OPC_devvars=[RCU_mask,Ant_mask,RCU_att,RCU_band,RCU_temp,RCU_pwrd,RCU_LED,RCU_ADC_lock,RCU_ADC_SYNC,RCU_ADC_JESD,RCU_ADC_CML,RCU_OUT1,RCU_OUT2,RCU_ID,RCU_VER,HBA_Delay,HBA_led,RCU_uCV_ID]
#OPC_devvars=[RCU_mask,Ant_mask,RCU_att,RCU_band,RCU_temp,RCU_pwrd,RCU_LED,RCU_uCV_ID,RCU_uCV_spd0,RCU_uCV_RXspd1,RCU_uCV_RXspd2,RCU_uCV_TXspd1,RCU_uCV_debug ]#,HBA1_Pwr]#,RCU_CNF1,RCU_CNF2]
#Instr=namedtuple("DevInstr","type dev nvalue value")
#Instrs=namedtuple("Instr","name ninstr instr")
@@ -115,46 +117,52 @@ RCU_init=Instrs("ReadRegisters",2,[
Instr(DevType.VarUpdate,RCU_OUT2,3,[0,0,0])
])
-ADC_on=Instrs("ADC_on",16,[
+ADC_on=Instrs("ADC_on",17,[
Instr(DevType.SPIbb,RCU_ADC1_JESD_ctr,1,[0x14]),
Instr(DevType.SPIbb,RCU_ADC1_CML_level,1,[0x7]),
Instr(DevType.SPIbb,RCU_ADC1_SYNC_ctr,1,[1]),
+ Instr(DevType.SPIbb,RCU_ADC1_PLL_enc,1,[0x8]),
Instr(DevType.SPIbb,RCU_ADC1_update,1,[1]),
+ Instr(DevType.Wait,0,0,[100]),
Instr(DevType.SPIbb,RCU_ADC2_JESD_ctr,1,[0x14]),
Instr(DevType.SPIbb,RCU_ADC2_CML_level,1,[0x7]),
Instr(DevType.SPIbb,RCU_ADC2_SYNC_ctr,1,[1]),
+ Instr(DevType.SPIbb,RCU_ADC2_PLL_enc,1,[0x8]),
Instr(DevType.SPIbb,RCU_ADC2_update,1,[1]),
+ Instr(DevType.Wait,0,0,[100]),
Instr(DevType.SPIbb,RCU_ADC3_JESD_ctr,1,[0x14]),
Instr(DevType.SPIbb,RCU_ADC3_CML_level,1,[0x7]),
Instr(DevType.SPIbb,RCU_ADC3_SYNC_ctr,1,[1]),
+ Instr(DevType.SPIbb,RCU_ADC3_PLL_enc,1,[0x8]),
Instr(DevType.SPIbb,RCU_ADC3_update,1,[1]),
+ Instr(DevType.Wait,0,0,[500]),
Instr(DevType.VarUpdate,RCU_ADC_SYNC,3,[0,0,0]),
Instr(DevType.VarUpdate,RCU_ADC_JESD,3,[0,0,0]),
Instr(DevType.VarUpdate,RCU_ADC_CML,3,[0,0,0]),
Instr(DevType.VarUpdate,RCU_ADC_lock,3,[0,0,0])
])
-RCU_on=Instrs("RCU_on",12,[
+RCU_on=Instrs("RCU_on",20,[
Instr(DevType.I2C,RCU_IO2_CONF1,1,[0]),
Instr(DevType.I2C,RCU_IO2_CONF2,1,[0]),
+ Instr(DevType.I2C,RCU_IO2_OUT1,1,[0x4A]),
+ Instr(DevType.I2C,RCU_IO2_OUT2,1,[0x55]),
+ Instr(DevType.Wait,0,0,[300]),
Instr(DevType.I2C,RCU_IO3_CONF1,1,[0]),
Instr(DevType.I2C,RCU_IO3_CONF2,1,[0]),
Instr(DevType.I2C,RCU_IO1_CONF1,1,[0]),
Instr(DevType.I2C,RCU_IO1_CONF2,1,[0]),
- Instr(DevType.I2C,RCU_IO2_OUT1,1,[0x4A]),
- Instr(DevType.I2C,RCU_IO2_OUT2,1,[0x55]),
Instr(DevType.I2C,RCU_IO3_OUT1,1,[0x15]),
Instr(DevType.I2C,RCU_IO3_OUT2,1,[0x47]),
Instr(DevType.I2C,RCU_IO1_OUT1,1,[0xCA]),
Instr(DevType.I2C,RCU_IO1_OUT2,1,[0xCA]),
-# Instr(DevType.VarUpdate,RCU_att,3,[0,0,0]),
+ Instr(DevType.Wait,0,0,[200]),
+ Instr(DevType.VarUpdate,RCU_att,3,[0,0,0]),
Instr(DevType.VarUpdate,RCU_pwrd,1,[0]),
Instr(DevType.VarUpdate,RCU_OUT1,3,[0,0,0]),
Instr(DevType.VarUpdate,RCU_OUT2,3,[0,0,0]),
-# Instr(DevType.Instr,ADC1_on,0,[]),
-# Instr(DevType.Instr,ADC2_on,0,[]),
-# Instr(DevType.Instr,ADC3_on,0,[])
-# Instr(DevType.VarUpdate,RCU_ADC_lock,3,[0,0,0])
+# Instr(DevType.Wait,0,0,[300]),
+ Instr(DevType.Instr,ADC_on,0,[])
])
RCU_off=Instrs("RCU_off",1,[
@@ -171,7 +179,7 @@ RCU_update=Instrs("RCU_update",11,[
# Instr(DevType.VarUpdate,RCU_VER,1,[0]*10),
Instr(DevType.VarUpdate,RCU_att,3,[0,0,0]),
Instr(DevType.VarUpdate,RCU_band,3,[0,0,0]),
- Instr(DevType.VarUpdate,RCU_LED,3,[0,0,0]),
+ Instr(DevType.VarUpdate,RCU_LED,1,[0]),
Instr(DevType.VarUpdate,RCU_ADC_SYNC,3,[0,0,0]),
Instr(DevType.VarUpdate,RCU_ADC_JESD,3,[0,0,0]),
Instr(DevType.VarUpdate,RCU_ADC_CML,3,[0,0,0]),
diff --git a/rcu/spibitbang1.py b/rcu/spibitbang1.py
index 14541d7..ca8fd30 100644
--- a/rcu/spibitbang1.py
+++ b/rcu/spibitbang1.py
@@ -109,21 +109,23 @@ def GetSPIbb2(SetI2C,GetI2C,RCUi,devs,value):
ADC_rw = 0x01 # 0 for write, 1 for read
data = ( ADC_rw << 15) + ( ADC_bytes << 13 ) + ADC_reg_address
+ Setbit(CLK,0)
Setbit(CS,0) #enable
bit_array = "{0:{fill}16b}".format(data, fill='0')
logging.debug(str(("SPI TX",bit_array)))
for bit in bit_array:
+ Setbit(CLK,0)
Setbit(SDIO,int(bit))
Setbit(CLK,1)
- Setbit(CLK,0)
- Setbit(CS,1) #disable
+# Setbit(CS,1) #disable
+ Setbit(SDIOdir,1) #input
+ Setbit(CLK,0)
# print("read byte")
- Setbit(SDIOdir,1) #input
- Setbit(CS,0) #enable
+# Setbit(CS,0) #enable
a=[0]
N=len(value)
for i in range(N): value[i]=0
diff --git a/scripts/ADCreset.py b/scripts/ADCreset.py
index b0f208a..1fe427c 100644
--- a/scripts/ADCreset.py
+++ b/scripts/ADCreset.py
@@ -1,13 +1,14 @@
from test_common import *
-RCUs=[0];
+RCUs=[2,3];
setRCUmask(RCUs)
callmethod("RCU_off")
+#exit()
time.sleep(1)
callmethod("RCU_on")
-callmethod("RCU_on")
-time.sleep(1)
-callmethod("ADC_on")
+#callmethod("RCU_on")
+#time.sleep(1)
+#callmethod("ADC_on")
disconnect();
diff --git a/scripts/CLK.py b/scripts/CLK.py
new file mode 100644
index 0000000..4dbf2b4
--- /dev/null
+++ b/scripts/CLK.py
@@ -0,0 +1,16 @@
+from test_common import *
+
+#callmethod("CLK_off")
+#time.sleep(1)
+
+callmethod("CLK_on")
+time.sleep(1)
+callmethod("CLK_PLL_setup")
+#exit()
+#time.sleep(1)
+#callmethod("RCU_on")
+#callmethod("RCU_on")
+#time.sleep(1)
+#callmethod("ADC_on")
+
+disconnect();
diff --git a/scripts/RCUupdate.py b/scripts/RCUupdate.py
index 42dde84..bf9b5ef 100644
--- a/scripts/RCUupdate.py
+++ b/scripts/RCUupdate.py
@@ -1,7 +1,9 @@
from test_common import *
-RCUs=[0];
+RCUs=[0,1,2,3];
setRCUmask(RCUs)
+#for RCU in RCUs:
+setAntmask(RCUs,[True,True,True])
callmethod("RCU_update")
diff --git a/scripts/SetHBAT_BF.py b/scripts/SetHBAT_BF.py
new file mode 100644
index 0000000..ada75d2
--- /dev/null
+++ b/scripts/SetHBAT_BF.py
@@ -0,0 +1,26 @@
+RCU=3
+HBAT=1 #HBAT on RCU 0..2
+#HBA=5; #HBA Element in HBAT
+#BFX=11 #delay in 0.5ns
+#BFY=BFX+1
+name="HBA_element_beamformer_delays"
+
+from test_common import *
+import numpy as np
+
+AntMask=[(x==HBAT) for x in range(3)]
+setAntmask([RCU],AntMask)
+
+i=(RCU*3+HBAT)*32
+
+val=get_value(name+"_R")
+print("old:",val[i:i+32])
+
+val[i:i+32]=np.array(range(32))[::]
+
+set_value(name+"_RW",val)
+time.sleep(1)
+val=get_value(name+"_R")
+print("new:",val[i:i+32])
+
+disconnect()
diff --git a/scripts/SetHBAT_LED.py b/scripts/SetHBAT_LED.py
new file mode 100644
index 0000000..8a7c090
--- /dev/null
+++ b/scripts/SetHBAT_LED.py
@@ -0,0 +1,28 @@
+RCU=3
+HBAT=1 #HBAT on RCU 0..2
+LED=1 #on
+name="HBA_element_led"
+
+from test_common import *
+import numpy as np
+
+AntMask=[(x==HBAT) for x in range(3)]
+setAntmask([RCU],AntMask)
+
+i=(RCU*3+HBAT)*32
+
+val=get_value(name+"_R")
+#print("old:",val)
+print("old:",val[i:i+32])
+for x in range(32):
+ val[i+x]=LED
+#val[i]=LED #Not needed for LED
+#val[i+1]=LED
+
+set_value(name+"_RW",val)
+time.sleep(1)
+val=get_value(name+"_R")
+#print("new:",val)
+print("new:",val[i:i+32])
+
+disconnect()
diff --git a/scripts/SetHBA_BF.py b/scripts/SetHBA_BF.py
index 263e91c..697a9a2 100644
--- a/scripts/SetHBA_BF.py
+++ b/scripts/SetHBA_BF.py
@@ -1,5 +1,5 @@
-RCU=0
-HBAT=1 #HBAT on RCU 0..2
+RCU=1
+HBAT=0 #HBAT on RCU 0..2
HBA=5; #HBA Element in HBAT
BFX=11 #delay in 0.5ns
BFY=BFX+1
diff --git a/scripts/SetHBA_LED.py b/scripts/SetHBA_LED.py
index 5cfc1b1..7869dac 100644
--- a/scripts/SetHBA_LED.py
+++ b/scripts/SetHBA_LED.py
@@ -1,7 +1,7 @@
-RCU=0
+RCU=1
HBAT=1 #HBAT on RCU 0..2
-HBA=5; #HBA Element in HBAT
-LED=1 #on
+HBA=14; #HBA Element in HBAT
+LED=0 #on
name="HBA_element_led"
from test_common import *
diff --git a/scripts/test_common.py b/scripts/test_common.py
index 40d6ba1..6df8d70 100644
--- a/scripts/test_common.py
+++ b/scripts/test_common.py
@@ -1,4 +1,5 @@
-Address="opc.tcp://odroidRCU2:4842/"
+#Address="opc.tcp://odroidRCU2:4842/"
+Address="opc.tcp://LTSpi:4842/"
import sys
sys.path.insert(0, "..")
import logging
@@ -36,9 +37,9 @@ def setRCUmask(rcu=[]):
name="RCU_mask_RW"
M=get_value(name)
print(name," old:",M)
- M=[0 for m in M]
+ M=[False for m in M]
for r in rcu:
- M[r]=1
+ M[r]=True
set_value(name,M)
print(name," new:",get_value(name))
--
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