diff --git a/clk/CLK.py b/clk/CLK.py index f71fe4de5f2eb5a48b97611a38ea03ca938c289c..37d9b6f4565e64896914a1c52758965a2dd08be6 100644 --- a/clk/CLK.py +++ b/clk/CLK.py @@ -380,8 +380,8 @@ class RCU1(): return RCUthread1 def Queue_Monitor(self,Q1,NRCU): -# Inst1=Vars.Instr(Vars.DevType.VarUpdate,Vars.RCU_temp,NRCU,[0]*NRCU) -# Q1.put(Inst1) + Inst1=Vars.Instr(Vars.DevType.VarUpdate,Vars.CLK_Stat1,NRCU,[0]*NRCU) + Q1.put(Inst1) # Inst1=Vars.Instr(Vars.DevType.VarUpdate,Vars.RCU_ADC_lock,96,[0]*96) # Q1.put(Inst1) return diff --git a/clk/HWconf.py b/clk/HWconf.py index b975665baded666250e115e29c9a372c03a72852..e6f2f6f3195f22279433b96ff6c92465bd453104 100644 --- a/clk/HWconf.py +++ b/clk/HWconf.py @@ -17,3 +17,15 @@ RCU_storeReg=4; #Number of stored registers SPIBB_PLL=BBdev(4,[CLK_IO3_OUT1,CLK_IO3_OUT1,CLK_IO3_OUT1,CLK_IO3_OUT1],[4,7,5,6],0) #CLK,SDI,SDO,CS CLK_PLL_lock =DevReg(SPIBB_PLL,0X00,0X00,0) # PLL locked status +CLK_PLL_div =DevReg(SPIBB_PLL,0X0D,0X0D,0) # PLL divide +CLK_PLL_pwr =DevReg(SPIBB_PLL,0X03,0X03,0) # PLL divide +CLK_PLL_5 =DevReg(SPIBB_PLL,0X05,0X05,0) # PLL divide +CLK_PLL_6 =DevReg(SPIBB_PLL,0X06,0X06,0) # PLL divide +CLK_PLL_7 =DevReg(SPIBB_PLL,0X07,0X07,0) # PLL divide +CLK_PLL_8 =DevReg(SPIBB_PLL,0X08,0X08,0) # PLL divide +CLK_PLL_9 =DevReg(SPIBB_PLL,0X09,0X09,0) # PLL divide +CLK_PLL_A =DevReg(SPIBB_PLL,0X0A,0X0A,0) # PLL divide +CLK_PLL_D =DevReg(SPIBB_PLL,0X0D,0X0D,0) # PLL divide +CLK_PLL_F =DevReg(SPIBB_PLL,0X0F,0X0F,0) # PLL divide +CLK_PLL_11 =DevReg(SPIBB_PLL,0X11,0X11,0) # PLL divide +CLK_PLL_13 =DevReg(SPIBB_PLL,0X13,0X13,0) # PLL divide diff --git a/clk/Vars.py b/clk/Vars.py index 7e4d4b02e5e8a06021fac03eacfc8abad5b0a01e..75c45b19b9158ad60b35a85b38132a0ade42ea03 100644 --- a/clk/Vars.py +++ b/clk/Vars.py @@ -3,23 +3,38 @@ from .HWconf import * CLKmod=I2Cmodules.CLK -CLK_IGNORE_PPS= VarArray("CLK_Ignore_PPS",1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT2,1 ,2,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_IGNORE_PPS= VarArray("CLK_Ignore_PPS",1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,1 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) CLK_Enable_PWR= VarArray("CLK_Enable_PWR",1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,1 ,1,1)],RW.ReadOnly,datatype.dInt,1,None,None) -CLK_Stat1 = VarArray("CLK_Stat" ,1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,1 ,2,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_Stat1 = VarArray("CLK_Stat" ,1,[Var2dev("",CLKmod,DevType.I2C,CLK_IO3_OUT1,2 ,2,1)],RW.ReadOnly,datatype.dInt,1,None,None) CLK_lock1 = VarArray("CLK_Lock" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_lock,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_div1 = VarArray("CLK_Div" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_div,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_pwr1 = VarArray("CLK_Pwr" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_pwr,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_5 = VarArray("CLK_PLL_5" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_5,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_6 = VarArray("CLK_PLL_6" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_6,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_7 = VarArray("CLK_PLL_7" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_7,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_8 = VarArray("CLK_PLL_8" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_8,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_9 = VarArray("CLK_PLL_9" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_9,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_A = VarArray("CLK_PLL_A" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_A,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_D = VarArray("CLK_PLL_D" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_D,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_F = VarArray("CLK_PLL_F" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_F,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_11 = VarArray("CLK_PLL_11" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_11,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) +CLK_13 = VarArray("CLK_PLL_13" ,1,[Var2dev("",CLKmod,DevType.SPIbb,CLK_PLL_13,8 ,0,1)],RW.ReadOnly,datatype.dInt,1,None,None) -OPC_devvars=[CLK_Enable_PWR,CLK_lock1] +#OPC_devvars=[CLK_Enable_PWR,CLK_Stat1,CLK_5,CLK_6,CLK_7,CLK_8,CLK_9,CLK_A,CLK_D,CLK_F,CLK_11,CLK_13] #,CLK_lock1,CLK_Stat1,CLK_div1,CLK_pwr1,CLK_IGNORE_PPS] +OPC_devvars=[CLK_Enable_PWR,CLK_Stat1] #,CLK_lock1,CLK_Stat1,CLK_div1,CLK_pwr1,CLK_IGNORE_PPS] -RCU_init=Instrs("ReadRegisters",2,[ - Instr(DevType.VarUpdate,CLK_IGNORE_PPS,1,[0]), - Instr(DevType.VarUpdate,CLK_Enable_PWR,1,[0]) +RCU_init=Instrs("CLK_update",2,[ +# Instr(DevType.VarUpdate,CLK_IGNORE_PPS,1,[0]), + Instr(DevType.VarUpdate,CLK_Enable_PWR,1,[0]), + Instr(DevType.VarUpdate,CLK_Stat1,1,[0]) ]) CLK_on=Instrs("CLK_on",3,[ - Instr(DevType.I2C,CLK_IO3_CONF1,1,[0x2C]), - Instr(DevType.I2C,CLK_IO3_OUT1 ,1,[0x42]), - Instr(DevType.VarUpdate,CLK_lock1,1,[0]), + Instr(DevType.I2C,CLK_IO3_CONF1,1,[0x2C]),#0010 1100 PPS/PWR output, SCLK,CS,SDI + Instr(DevType.I2C,CLK_IO3_OUT1 ,1,[0x42]),#0100 0010 high:PWR enable, CS +# Instr(DevType.VarUpdate,CLK_lock1,1,[0]), + Instr(DevType.VarUpdate,CLK_Stat1,1,[0]), Instr(DevType.VarUpdate,CLK_Enable_PWR,1,[0]) ]) @@ -35,20 +50,25 @@ def SPIinst(reg,value): CLK_PLL_setup=Instrs("CLK_PLL_setup",15,[ # SPIinst(0x03,0x08), # Instr(DevType.I2C,CLK_IO3_CONF1,1,[0x2C]), - SPIinst(0x05,0x97), + SPIinst(0x05,0x17),#was 97 SPIinst(0x06,0x10), + SPIinst(0x07,0x04), SPIinst(0x08,0x01), SPIinst(0x07,0x00), + SPIinst(0x09,0x10), SPIinst(0x0A,0x14), SPIinst(0x09,0x00), + SPIinst(0x0D,0x01),#was 2 SPIinst(0x0F,0x01), SPIinst(0x11,0x01), SPIinst(0x13,0x01), - Instr(DevType.VarUpdate,CLK_lock1,1,[0]) + # Instr(DevType.VarUpdate,CLK_lock1,1,[0]), + # Instr(DevType.VarUpdate,CLK_div1,1,[0]), + Instr(DevType.VarUpdate,CLK_Stat1,1,[0]) ]) -OPC_methods=[CLK_on,CLK_off,CLK_PLL_setup] +OPC_methods=[CLK_on,CLK_off,CLK_PLL_setup,RCU_init] diff --git a/pypcc2.py b/pypcc2.py index 4c873a2909dcd12b887880178b0738adfef8aec3..b7b716828ce4778cc51c23b4322e85ea8bc4a9d4 100644 --- a/pypcc2.py +++ b/pypcc2.py @@ -66,6 +66,7 @@ RCUthread1=RCU.start(Q1) CLKthread1=CLK.start(Q2) RunTimer=True; + def TimerThread(Q1,RCU): V1=opcuaserv.AddVar("RCU_monitor_rate_RW",30) cnt=0;#Count second ticks @@ -86,6 +87,27 @@ def TimerThread(Q1,RCU): Timerthread1 = threading.Thread(target=TimerThread, args=(Q1,RCU)) Timerthread1.start() + +def Timer2Thread(Q1,RCU): + V1=opcuaserv.AddVar("CLK_monitor_rate_RW",10) + cnt=0;#Count second ticks + while RunTimer: + time.sleep(1) + T1=V1.get_data_value().Value.Value + if T1==0: + continue; + cnt+=1; + if cnt>=T1: + if Q1.qsize()>3: continue; + cnt=0; + logging.debug(str(("I2C bytes=",I2C.I2Ccounter," Qlength=",Q1.qsize()))) + RCU.Queue_Monitor(Q1,1) + + logging.info("End Timer thread") + +Timerthread2 = threading.Thread(target=Timer2Thread, args=(Q2,CLK)) +Timerthread2.start() + # on SIGINT: stop thread(s) by adding None to instruction queue(s) def signal_handler(sig, frame): logging.info('Stop RCU thread') @@ -109,3 +131,4 @@ finally: RCUthread1.join() CLKthread1.join() Timerthread1.join() + Timerthread2.join() diff --git a/rcu/Vars.py b/rcu/Vars.py index 1f44489e2eb1ca1e6227e97c81fc2c96441d71a2..7467d6bafa94a9ba86698e6e6f566a09d7dee1bd 100644 --- a/rcu/Vars.py +++ b/rcu/Vars.py @@ -168,14 +168,16 @@ RCU_on=Instrs("RCU_on",20,[ Instr(DevType.VarUpdate,RCU_att,3,[0,0,0]), Instr(DevType.VarUpdate,RCU_pwrd,1,[0]), Instr(DevType.VarUpdate,RCU_OUT1,3,[0,0,0]), - Instr(DevType.VarUpdate,RCU_OUT2,3,[0,0,0]), + Instr(DevType.VarUpdate,RCU_OUT2,3,[0,0,0]) # Instr(DevType.Wait,0,0,[300]), - Instr(DevType.Instr,ADC_on,0,[]) +# Instr(DevType.Instr,ADC_on,0,[]) ]) RCU_off=Instrs("RCU_off",1,[ # Instr(DevType.Var,RCU_mask,4,[1,1,1,1]), Instr(DevType.Var,RCU_pwrd,32,[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]), + Instr(DevType.I2C,RCU_IO3_OUT1,1,[0x0]), + Instr(DevType.I2C,RCU_IO3_OUT2,1,[0x0]), # Instr(DevType.Var,RCU_mask,4,[0,0,0,0]) ])