diff --git a/RCUdither.py b/I2Cbitbang.py similarity index 99% rename from RCUdither.py rename to I2Cbitbang.py index 0b05a7aeac9570d38830898365a5f4c75cced7a4..089c16a7b28261b72f62ad0aedb8a7bc5d051252 100644 --- a/RCUdither.py +++ b/I2Cbitbang.py @@ -1,7 +1,7 @@ from I2Cdevices import *; import numpy as np -class RCUdither(I2Cdevices): +class I2Cbitbang(I2Cdevices): def I2CSet(self,dev,reg,value,I2Ccallback,width=8,bitoffset=0): # def I2Cset(self,D,name,reg,data,I2Ccallback,dev_number=0): Dev=Find(self.D['I2C_devices'],'dev_name',dev) diff --git a/LTS_RCU2L.yaml b/LTS_RCU2L.yaml index 084d6e589bdab6a9d2bd79415fc1bbf4be7c9d4e..03ce80441325522d175a29a6a123e8bba371947c 100644 --- a/LTS_RCU2L.yaml +++ b/LTS_RCU2L.yaml @@ -1,6 +1,6 @@ dev_children: - child_name: Dither3 - child_dev : RCUdither + child_dev : I2Cbitbang child_conf: LTS_RCU2_dither child_GPIO: - SCL : IO1.OUT1.6 @@ -8,7 +8,7 @@ dev_children: - SDI : IO2.IN2.3 - SDIOdir : IO2.CONF2.3 - child_name: Dither2 - child_dev : RCUdither + child_dev : I2Cbitbang child_conf: LTS_RCU2_dither child_GPIO: - SCL : IO1.OUT2.7 @@ -16,7 +16,7 @@ dev_children: - SDI : IO1.IN1.7 - SDIOdir : IO1.CONF1.7 - child_name: ADC1 - child_dev : RCUADC + child_dev : SPIbitbang1 child_conf: LTS_RCU2_ADC child_GPIO: - CLK : IO3.OUT1.1 @@ -25,7 +25,7 @@ dev_children: - SDIOdir: IO3.CONF1.0 - CS : IO3.OUT2.0 - child_name: ADC2 - child_dev : RCUADC + child_dev : SPIbitbang1 child_conf: LTS_RCU2_ADC child_GPIO: - CLK : IO3.OUT1.3 @@ -34,7 +34,7 @@ dev_children: - SDIOdir: IO3.CONF1.2 - CS : IO3.OUT2.1 - child_name: ADC3 - child_dev : RCUADC + child_dev : SPIbitbang1 child_conf: LTS_RCU2_ADC child_GPIO: - CLK : IO3.OUT1.5 diff --git a/LTS_RCU2dig.yaml b/LTS_RCU2dig.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2f9c9ee5f16e668149a517872752236a8a4f59fb --- /dev/null +++ b/LTS_RCU2dig.yaml @@ -0,0 +1,212 @@ +dev_children: + - child_name: ADC1 + child_dev : SPIbitbang1 + child_conf: LTS_RCU2_ADC + child_GPIO: + - CLK : IO3.OUT1.1 + - SDO : IO3.OUT1.0 + - SDI : IO3.IN1.0 + - SDIOdir: IO3.CONF1.0 + - CS : IO3.OUT2.0 + - child_name: ADC2 + child_dev : SPIbitbang1 + child_conf: LTS_RCU2_ADC + child_GPIO: + - CLK : IO3.OUT1.3 + - SDO : IO3.OUT1.2 + - SDI : IO3.IN1.2 + - SDIOdir: IO3.CONF1.2 + - CS : IO3.OUT2.1 + - child_name: ADC3 + child_dev : SPIbitbang1 + child_conf: LTS_RCU2_ADC + child_GPIO: + - CLK : IO3.OUT1.5 + - SDO : IO3.OUT1.4 + - SDI : IO3.IN1.4 + - SDIOdir: IO3.CONF1.4 + - CS : IO3.OUT2.2 + +#This is the I2C devices in the RCU +I2C_devices: + - dev_name: IO1 + dev_description: IO-Expander for filter selection + dev_address: 0x75 + dev_device: TCA9539 + dev_registers: + - reg_name: CONF1 + reg_addr: 6 + - reg_name: CONF2 + reg_addr: 7 + - reg_name: OUT1 + reg_addr: 2 + ref_default: 0 + - reg_name: OUT2 + reg_addr: 3 + ref_default: 0 + - reg_name: IN1 + reg_addr: 0 + - reg_name: IN2 + reg_addr: 1 + + - dev_name: IO3 + dev_description: IO-Expander for ADC control + dev_address: 0x20 + dev_device: TCA6416 + dev_registers: + - reg_name: CONF1 + reg_description: Direction of IO pins 0..7 + reg_addr: 6 + - reg_name: CONF2 + reg_description: Direction of IO pints 8..15 + reg_addr: 7 + - reg_name: IN1 + reg_description: Ouput port register 0..7 + reg_addr: 0 + - reg_name: IN2 + reg_description: Ouput port register 0..7 + reg_addr: 1 + - reg_name: OUT1 + reg_description: Ouput port register 0..7 + reg_addr: 2 + reg_default: 0x0F + - reg_name: OUT2 + reg_description: Ouput port register 8..15 + reg_addr: 3 + reg_default: 0x0F + + - dev_name: IO2 + dev_description: IO-Expander for ON/OFF, Band, BUFx2 + dev_address: 0x76 + dev_device: TCA9539 + dev_registers: + - reg_name: CONF1 + reg_addr: 6 + - reg_name: CONF2 + reg_addr: 7 + - reg_name: OUT1 + reg_addr: 2 + ref_default: 0 + - reg_name: OUT2 + reg_addr: 3 + ref_default: 0 + - reg_name: IN1 + reg_addr: 0 + - reg_name: IN2 + reg_addr: 1 + + - dev_name: UC + dev_description: RCU microcontroller + dev_address: 0x40 + dev_registers: + - reg_name: ID + reg_description: Device ID + reg_addr: 0 + + - dev_name: ROM + dev_description: EEPROM memory + dev_address: 0x53 + dev_registers: + - reg_name: ctr_len + reg_description: Length of control data + reg_addr: 0 + - reg_name: ctr_dat + reg_description: Control data (protocol buffers) + reg_addr: 2 + + + - dev_name: AN + dev_description: Monitor ADC on RCU + dev_address: 0x14 + dev_device: LTC2495 + dev_registers: + - reg_name: Ch0 + reg_addr: 0xB080 + - reg_name: Ch1 + reg_addr: 0xB8 + - reg_name: Ch2 + reg_addr: 0xB1 + - reg_name: Ch3 + reg_addr: 0xB9 + - reg_name: Ch4 + reg_addr: 0xB2 + - reg_name: Ch5 + reg_addr: 0xBA + - reg_name: Ch6 + reg_addr: 0xB3 + - reg_name: Ch7 + reg_addr: 0xBB + - reg_name: Temp + reg_addr: 0xA0C0 + +Variables: + - var_name: Attenuator1 + var_dev: IO1.OUT1 + var_width: 5 + var_max: 21 + var_R/W: RW + - var_name: Attenuator2 + var_dev: IO1.OUT2 + var_width: 5 + var_max: 21 + var_R/W: RW + - var_name: Attenuator3 + var_dev: IO2.OUT1 + var_width: 5 + var_max: 24 + var_R/W: RW + + - var_name: Pwr_dig + var_description: Enable LDOs + var_dict: {0 : Off, 1 : On} + var_dev: IO2.OUT1 + var_width: 1 + var_bitoffset: 6 + var_R/W: RO + + - var_name: LED0 + var_description: Front panel LEDs, 0=On + var_dict: {0 : Off, 1 : Yellow, 2: Red, 3: Orange} + var_dev: IO2.OUT2 + var_width: 2 + var_bitoffset: 6 + var_R/W: RW + + - var_name: Temperature + var_dev: AN.Temp + var_width: 23 + var_scale: 4.21e-3 + var_R/W: RO + + + +Methods: + - method_name: RCU_on + registers: + - IO2.CONF1: [0] #Setup IO expanders to output with default values + - IO2.OUT1: [0x4A] + - IO2.OUT2: [0x55] + - IO3.OUT1: [0x7f] + - IO3.OUT2: [0x47] + - IO1.OUT1: [0xCA] + - IO1.OUT2: [0xCA] + - IO2.CONF2: [0] + - IO3.CONF1: [0] + - IO3.CONF2: [0] + - IO1.CONF1: [0] + - IO1.CONF2: [0] + - ADC1_Setup: 1 + - ADC2_Setup: 1 + - ADC3_Setup: 1 + + - method_name: RCU_off + registers: + - IO2.OUT1: [0x00] #Switch all off + - IO2.OUT2: [0x00] + - IO3.OUT1: [0x00] + - IO3.OUT2: [0x00] + - IO1.OUT1: [0x00] + - IO1.OUT2: [0x00] + + + diff --git a/LTS_clk.yaml b/LTS_clk.yaml index bde2d570b7708b19d015a04bd861e9868212ed22..cb4572b3583ac9b643b51d9a39a5f59195f2eaf1 100644 --- a/LTS_clk.yaml +++ b/LTS_clk.yaml @@ -1,6 +1,6 @@ dev_children: - child_name: PLL - child_dev : clkPLL + child_dev : SPIbitbang2 child_conf: LTS_clkPLL child_GPIO: - CLK : IO3.OUT1.4 diff --git a/LTS_switch.yaml b/LTS_switch.yaml index b3ccc67b97a8ae78d2d41e1a0c8007418de681bf..510cb8c2fcbd0857555d195a9233df389a1d3cef 100644 --- a/LTS_switch.yaml +++ b/LTS_switch.yaml @@ -10,11 +10,11 @@ dev_children: child_addr: 1 - child_name: RCU02 child_dev: I2Cdevices - child_conf: LTS_RCU2L + child_conf: LTS_RCU2dig child_addr: 2 - child_name: RCU03 child_dev: I2Cdevices - child_conf: LTS_RCU2L + child_conf: LTS_RCU2dig child_addr: 3 - child_name: CLK child_dev: I2Cdevices diff --git a/README.md b/README.md index 658f87dd659c3c4f09880eba4706bd8bcbd4af3a..85fb769803b61180b6192e491a9df99c41944124 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,5 @@ # PyPCC Python OPC-UA server to control the I2C devices in the LTS. + ++ opcuserv.py: OPC-UA server that expose (visible) variables and methods. diff --git a/RCUADC.py b/SPIbitbang1.py similarity index 98% rename from RCUADC.py rename to SPIbitbang1.py index 186ff40ca2f261ed2b41c14e5bf8eb8c07ba5f26..6da8c4509751908c1b3a3a50cf05f6681c91e15d 100644 --- a/RCUADC.py +++ b/SPIbitbang1.py @@ -1,7 +1,7 @@ from I2Cdevices import *; import numpy as np -class RCUADC(I2Cdevices): +class SPIbitbang1(I2Cdevices): def I2CSet(self,dev,reg,value,I2Ccallback,width=8,bitoffset=0): SPI=Find(self.D['I2C_devices'],'dev_name',dev) Reg=Find(SPI['dev_registers'],'reg_name',reg) diff --git a/clkPLL.py b/SPIbitbang2.py similarity index 98% rename from clkPLL.py rename to SPIbitbang2.py index 2e8e6dab1cd1b2ce3057879c234b013e2ba250d2..bc12db43a7899d5269a2c0938c7f23df367a5131 100644 --- a/clkPLL.py +++ b/SPIbitbang2.py @@ -1,7 +1,7 @@ from I2Cdevices import *; import numpy as np -class clkPLL(I2Cdevices): +class SPIbitbang2(I2Cdevices): def I2CSet(self,dev,reg,value,I2Ccallback,width=8,bitoffset=0): SPI=Find(self.D['I2C_devices'],'dev_name',dev) Reg=Find(SPI['dev_registers'],'reg_name',reg) diff --git a/pypcc_test.py b/pypcc_test.py new file mode 100644 index 0000000000000000000000000000000000000000..e06e28a82a7d71484a7cbcfe7c49471b1eaeae4b --- /dev/null +++ b/pypcc_test.py @@ -0,0 +1,22 @@ +from hwdev import hwdev; +import time + +def I2C1server(addr,data,reg=None,read=0): + return True; + +class pypcc(hwdev): + def GetVarValue(self,name,value): + for cname,child in self.children: + if not(child.GetVarValue(name,value,I2C1server)): return False + return True + + def SetVarValue(self,name,value): + for cname,child in self.children: + if not(child.SetVarValue(name,value,I2C1server)): return False + return True + + + def CallMethod(self,name,params): + for cname,child in self.children: + child.CallMethod(name,params,I2C1server) + return True; diff --git a/test2.py b/test2.py index 1ea4ec5d623d0696a138f866c1d41a95575b3ed5..b780d8ccd71c9334c46a6112a83ab0dc628a9d65 100644 --- a/test2.py +++ b/test2.py @@ -1,4 +1,5 @@ -import pypcc; +#import pypcc; +import pypcc_test as pypcc; P1=pypcc.pypcc("LTS_pypcc.yaml")