From 6640552793af33c1e969ed433cc7b89ba88fd19d Mon Sep 17 00:00:00 2001
From: kruger <kruger@astron.nl>
Date: Mon, 28 Jun 2021 10:24:01 +0200
Subject: [PATCH] CRC enabled on all POLs
---
config/UNB2TR.yaml | 134 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 114 insertions(+), 20 deletions(-)
diff --git a/config/UNB2TR.yaml b/config/UNB2TR.yaml
index bba9b7e..101d468 100644
--- a/config/UNB2TR.yaml
+++ b/config/UNB2TR.yaml
@@ -91,18 +91,105 @@ device_registers:
address: 0x2C
driver: I2C_switch2
registers:
- - name: TEMP
- address: 0x8D
- crc: True
- - name: VIN
- address: 0x88
- crc: True
- - name: VOUT
- address: 0x8B
- crc: True
- - name: IOUT
- address: 0x8C
- crc: True
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_CORE
+ address: 0x1
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_ERAM
+ address: 0xD
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_RXGXB
+ address: 0xE
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_TXGXB
+ address: 0xF
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_HGXB
+ address: 0x10
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_PGM
+ address: 0x11
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_QSFP0
+ address: 0x2
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_QSFP1
+ address: 0x1
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_SW1V2
+ address: 0xF
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_SWPHY
+ address: 0xE
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_CLOCK
+ address: 0xD
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
variables:
@@ -226,7 +313,8 @@ variables:
- name: [UNB2_POL_QSFP_N01_VOUT,UNB2_POL_QSFP_N23_VOUT]
driver: switch_PS
- devreg: [0x2.0x8B,0x1.0x8B]
+# devreg: [0x2.0x8B,0x1.0x8B]
+ devreg: [POL_QSFP0.VOUT,POL_QSFP1.VOUT]
width: 16
rw: ro
dtype: double
@@ -237,7 +325,8 @@ variables:
- name: [UNB2_POL_SWITCH_1V2_VOUT,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_CLOCK_VOUT]
driver: switch_PS
- devreg: [0xF.0x8B,0xE.0x8B,0xD.0x8B]
+# devreg: [0xF.0x8B,0xE.0x8B,0xD.0x8B]
+ devreg: [POL_SW1V2.VOUT,POL_SWPHY.VOUT,POL_CLOCK.VOUT]
width: 16
rw: ro
dtype: double
@@ -248,7 +337,8 @@ variables:
- name: [UNB2_DC_DC_48V_12V_IOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
driver: switch_PS
- devreg: [DC_DC.IOUT,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
+# devreg: [DC_DC.IOUT,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
+ devreg: [DC_DC.IOUT,POL_QSFP0.IOUT,POL_QSFP1.IOUT,POL_SW1V2.IOUT,POL_SWPHY.IOUT,POL_CLOCK.IOUT]
width: 16
rw: ro
dtype: double
@@ -258,7 +348,8 @@ variables:
- name: [UNB2_DC_DC_48V_12V_TEMP,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_TEMP,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
driver: switch_PS
- devreg: [DC_DC.TEMP,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
+# devreg: [DC_DC.TEMP,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
+ devreg: [DC_DC.TEMP,POL_QSFP0.TEMP,POL_QSFP1.TEMP,POL_SW1V2.TEMP,POL_SWPHY.TEMP,POL_CLOCK.TEMP]
width: 16
rw: ro
dtype: double
@@ -290,7 +381,8 @@ variables:
- name: [UNB2_FPGA_POL_CORE_IOUT,UNB2_FPGA_POL_ERAM_IOUT,UNB2_FPGA_POL_RXGXB_IOUT,UNB2_FPGA_POL_TXGXB_IOUT,UNB2_FPGA_POL_HGXB_IOUT,UNB2_FPGA_POL_PGM_IOUT]
driver: switch_FPGA_PS
- devreg: [0x1.0x8C,0xD.0x8C,0xE.0x8C,0xF.0x8C,0x10.0x8C,0x11.0x8C]
+# devreg: [0x1.0x8C,0xD.0x8C,0xE.0x8C,0xF.0x8C,0x10.0x8C,0x11.0x8C]
+ devreg: [POL_CORE.IOUT,POL_ERAM.IOUT,POL_RXGXB.IOUT,POL_TXGXB.IOUT,POL_HGXB.IOUT,POL_PGM.IOUT]
width: 16
rw: ro
dtype: double
@@ -301,7 +393,8 @@ variables:
- name: [UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_TEMP,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_TEMP,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_TEMP]
driver: switch_FPGA_PS
- devreg: [0x1.0x8D,0xD.0x8D,0xE.0x8D,0xF.0x8D,0x10.0x8D,0x11.0x8D]
+# devreg: [0x1.0x8D,0xD.0x8D,0xE.0x8D,0xF.0x8D,0x10.0x8D,0x11.0x8D]
+ devreg: [POL_CORE.TEMP,POL_ERAM.TEMP,POL_RXGXB.TEMP,POL_TXGXB.TEMP,POL_HGXB.TEMP,POL_PGM.TEMP]
width: 16
rw: ro
dtype: double
@@ -312,7 +405,7 @@ variables:
- name: [UNB2_FPGA_POL_CORE_VOUT]
driver: switch_FPGA_PS
- devreg: [0x1.0x8B]
+ devreg: [POL_CORE.VOUT]
width: 16
rw: ro
dtype: double
@@ -324,7 +417,8 @@ variables:
- name: [UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_PGM_VOUT]
driver: switch_FPGA_PS
- devreg: [0xD.0x8B,0xE.0x8B,0xF.0x8B,0x10.0x8B,0x11.0x8B]
+ devreg: [POL_ERAM.VOUT,POL_RXGXB.VOUT,POL_TXGXB.VOUT,POL_HGXB.VOUT,POL_PGM.VOUT]
+# devreg: [0xD.0x8B,0xE.0x8B,0xF.0x8B,0x10.0x8B,0x11.0x8B]
width: 16
rw: ro
dtype: double
--
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