diff --git a/config/UNB2TR.yaml b/config/UNB2TR.yaml
index 85c24cf916c2beac018bd1b681f4947ee57b7e94..bba9b7e29b70df02c98ede1d6aa6417425db0552 100644
--- a/config/UNB2TR.yaml
+++ b/config/UNB2TR.yaml
@@ -87,6 +87,23 @@ device_registers:
     store: True
 
 
+- name: DC_DC
+  address: 0x2C
+  driver: I2C_switch2
+  registers:
+  - name: TEMP
+    address: 0x8D
+    crc: True
+  - name: VIN
+    address: 0x88
+    crc: True
+  - name: VOUT
+    address: 0x8B
+    crc: True
+  - name: IOUT
+    address: 0x8C
+    crc: True
+
 variables:
 
 #When I2C bus timeout, bus_error set to False.  Can we set to True again to retry.
@@ -188,7 +205,7 @@ variables:
 
    - name: [UNB2_DC_DC_48V_12V_VIN,UNB2_DC_DC_48V_12V_VOUT]
      driver: switch_PS
-     devreg:  [0x2C.0x88,0x2C.0x8B]
+     devreg:  [DC_DC.VIN,DC_DC.VOUT]
      width: 16
      rw:  ro
      dtype: double
@@ -231,7 +248,7 @@ variables:
 
    - name: [UNB2_DC_DC_48V_12V_IOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
      driver: switch_PS
-     devreg:  [0x2C.0x8C,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
+     devreg:  [DC_DC.IOUT,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
      width: 16
      rw:  ro
      dtype: double
@@ -241,7 +258,7 @@ variables:
 
    - name: [UNB2_DC_DC_48V_12V_TEMP,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_TEMP,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
      driver: switch_PS
-     devreg:  [0x2C.0x8D,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
+     devreg:  [DC_DC.TEMP,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
      width: 16
      rw:  ro
      dtype: double
diff --git a/i2cserv/i2c_array.py b/i2cserv/i2c_array.py
index 2f083635893a153ff8f438840b35054cf767245b..379ad08b7ce193b3c201b4388ffac3c68cec34de 100644
--- a/i2cserv/i2c_array.py
+++ b/i2cserv/i2c_array.py
@@ -201,7 +201,7 @@ class i2c_array(i2c_dev):
             return devreg['drivercls'].i2csetget(devreg['addr'],value,reg=devreg['register_W'])
 
     def GetVarValue(self,devreg,width,bitoffset,value,mode=0):
-        logging.debug(str(("RCU1 Get ",self.RCUi,devreg['addr'],value)))
+        logging.debug(str(("GetVarValue",self.RCUi,devreg['addr'],value,mode)))
 #                self.GetI2C(RCUi,devreg,width,bitoffset,value)
 #        if dev.store>0:
 #            value[0]=self.previous[RCUi,dev.store-1]
@@ -229,7 +229,8 @@ class i2c_array(i2c_dev):
             callback(0,[250],read=3)
             if not(callback(devreg['addr'],value2,read=1)): return False;
           else:
-            if not(callback(devreg['addr'],value2,reg=reg,read=1)): return False;
+            rd=(5 if devreg.get('crc') else 1)
+            if not(callback(devreg['addr'],value2,reg=reg,read=rd)): return False;
         if value2[0] is None:  return False
         value[:]=value2[:];
         if devreg.get('store'):
diff --git a/i2cserv/i2c_smbus.py b/i2cserv/i2c_smbus.py
index a0b6efc03f2ac02a76936632b669500e9ad0ff9c..9a45b9d57f7f6333936f62646afab9e7f3274aed 100644
--- a/i2cserv/i2c_smbus.py
+++ b/i2cserv/i2c_smbus.py
@@ -9,6 +9,28 @@ import logging
 #read=2: write to register (common in group)
 #read=3: wait ms second
 from .hwdev import hwdev;
+CRClookup=[
+ 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15, 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
+ 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65, 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
+ 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5, 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
+ 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85, 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
+ 0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2, 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
+ 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2, 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
+ 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32, 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
+ 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42, 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
+ 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C, 0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
+ 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC, 0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
+ 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C, 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
+ 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C, 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
+ 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B, 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
+ 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B, 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
+ 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB, 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
+ 0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB, 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3]
+
+def crc8(data,crc=0):
+ for byte in data:
+   crc=CRClookup[crc ^ byte]
+ return crc
 
 class i2c_smbus(hwdev):
     def __init__(self,config):
@@ -21,6 +43,7 @@ class i2c_smbus(hwdev):
 
     def i2csetget(self,addr,data,reg=None,read=0):
        try:
+#              self.bus.pec=False
 #       if True:
               if read==3:
                      time.sleep(data[0]/1000.)
@@ -40,6 +63,19 @@ class i2c_smbus(hwdev):
                        for i in range(length):
                           data[i]=self.bus.read_byte(addr) #Not vey efficient!!
                      logging.debug(str(("I2C get",addr,reg,data,read)))
+              elif read==5:
+#                     self.bus.pec=True
+                     if not(reg is None):
+                           crc=crc8([(addr<<1)+0,reg,(addr<<1)+1])
+                           data2=self.bus.read_i2c_block_data(addr, reg, length+1)
+                           data[:]=data2[:-1]
+                           crc=crc8(data,crc)
+                           if not(crc==data2[-1]): 
+                                    logging.warning("CRC error")
+                                    return False;
+#                           print("CRC",hex(addr),hex(reg),[hex(x) for x in data],hex(data2[-1]),hex(crc))
+                     else: logging.warning("SMBUS crc without register not implemented!")
+                     logging.debug(str(("I2C get",addr,reg,data,read)))
               else:
                      if not(reg is None): 
                             self.bus.write_i2c_block_data(addr, reg, data)
diff --git a/yamlconfig.py b/yamlconfig.py
index b5ae7a670978b107966d0f6301511c8b7e927286..f0c304e78ff994b418b471d0c17b293437ccc8c5 100644
--- a/yamlconfig.py
+++ b/yamlconfig.py
@@ -79,6 +79,7 @@ class yamlconfig():
               if dev1: 
                     store=dev1.get('store',False)
                     wait=dev1.get('wait',0)
+                    crc=dev1.get('crc',False)
                     devcls=dev1.get('driver');
                     if not(devcls): logging.error("Can not find driver for register "+name2[0]);
                     else:
@@ -87,7 +88,7 @@ class yamlconfig():
                        else:
                          devcls=devcls.get('obj')
 #                    print(dev1)
-                    return {"addr":dev1.get('address',0),"register_R":str2int(name2[1]),"register_W":str2int(name2[1]),"store":store,"drivercls":devcls,"wait":wait};
+                    return {"addr":dev1.get('address',0),"register_R":str2int(name2[1]),"register_W":str2int(name2[1]),"store":store,"drivercls":devcls,"wait":wait,"CRC":crc};
               else: return {"addr":str2int(name2[0]),"register_R":str2int(name2[1]),"register_W":str2int(name2[1])}
           logging.error("Can not find device register "+str(name));
 #        except:
@@ -115,8 +116,9 @@ class yamlconfig():
                     regW=GetField(reg,'address',1,0)
                     store=reg.get('store',False)
                     wait=reg.get('wait',0)
+                    crc=reg.get('crc',0)
                     devregname=name2+'.'+reg['name'];
-                    devreglist[devregname]={"addr":addr,"register_R":regR,"register_W":regW,"store":store,"driver":devid,"wait":wait};
+                    devreglist[devregname]={"addr":addr,"register_R":regR,"register_W":regW,"store":store,"driver":devid,"wait":wait,"crc":crc};
 #                    print(devregname,devreglist[devregname]['addr'],devreglist[devregname]['register_R'],devreglist[devregname]['register_W']);
         self.devreglist=devreglist;
         for D in drivers: