diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index d46497dbc2a8e4bd592843ded465624b29adfc66..b7b2db13cb5fbb0cb49a9dd5de54a41cb0bc522b 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,5 +1,16 @@
-stages:
+stages:
+ - run
- image
+
+test-run:
+ stage: run
+ image: python:3.11
+ before_script:
+ - pip3 install -r requirements.txt
+ - python3 setup.py install
+ script:
+ - hwtr -h
+
docker-build:
stage: image
image: docker:latest
diff --git a/howtogit.txt b/howtogit.txt
new file mode 100644
index 0000000000000000000000000000000000000000..f931006a1e23579de14b99d67fc79fbc0f0b3307
--- /dev/null
+++ b/howtogit.txt
@@ -0,0 +1,8 @@
+1. Make dynamic tunnel from pi to local machine (kruger@dop416 in this example)
+On LCU: (pi can not ssh to LCU, so we need reverse ssh)
+ ssh -R 20222:dop416:22 pi@10.99.0.101
+then on pi: (dynamic tunnel)
+ ssh kruger@localhost -p 20222 -D 1080
+
+2. Configure git to use tunnel
+ git config http.proxy socks5h://localhost:1080
\ No newline at end of file
diff --git a/pypcc/config/APSCTTR.yaml b/pypcc/config/APSCTTR.yaml
index 512d1caad9b7a5271f29e9f298ff2df848c8bff1..a9b246da1335888fbcb04ba3098cc45b1ccc6395 100644
--- a/pypcc/config/APSCTTR.yaml
+++ b/pypcc/config/APSCTTR.yaml
@@ -9,17 +9,21 @@ drivers:
type: i2c_dev #I2C devices
parent: I2C
status: APSCTTR_I2C_error
- - name: SPIbb1
- type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
+ - name: SPIbb1
+ type: spibitbang3 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
parent: I2C_CLK
devreg: [IO1.GPIO1,IO1.GPIO1,IO1.GPIO1,IO1.GPIO1]
parameters: [4,7,5,6]
- name: SPIbb2
- type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
+ type: spibitbang3 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
parent: I2C_CLK
devreg: [IO2.GPIO1,IO2.GPIO1,IO2.GPIO1,IO2.GPIO1]
parameters: [4,7,5,6]
+ - name: LMP_GPIO
+ type: gpio_id
+ parameters: [21,20,16,12,7,8]
+
#This is the I2C devices in the RCU
device_registers:
- name: IO
@@ -44,8 +48,12 @@ device_registers:
description: Input/Ouput port 2
address: [1,3] #Read / Write address different
store: True
+ - name: POL1
+ address: 4
+ - name: POL2
+ address: 5
- - name: PLL2
+ - name: PLL2 #200MHz on IO1
driver: SPIbb1
registers:
- name: PLL_stat
@@ -129,6 +137,14 @@ variables:
dtype: boolean
dim: 1
+ - name: LMP_ID
+ driver: LMP_GPIO
+ devreg: ROM.ID #this is ignored
+ width: 6
+ rw: ro
+ dtype: uint8
+
+
- name: APSCT_PCB_ID
description: Unique PCB ID
driver: I2C_CLK
@@ -210,23 +226,52 @@ variables:
bitoffset: 3
width: 1
- - name: APSCT_PLL_200MHz_locked_SPI
- description: 0x81=locked
+ - name: APSCT_PLL_200MHz_lol
+ rw: ro
+ dtype: boolean
+# convert_unit: bool_invert
+ monitor: true
driver: I2C_CLK
- devreg: PLL2.PLL_stat
- width: 8
+ devreg: IO2.GPIO2
+ bitoffset: 4
+ width: 1
+
+ - name: APSCT_PLL_160MHz_lol
rw: ro
- dtype: uint8
- debug: True
+ dtype: boolean
+# convert_unit: bool_invert
+ monitor: true
+ driver: I2C_CLK
+ devreg: IO2.GPIO2
+ bitoffset: 5
+ width: 1
- - name: APSCT_PLL_160MHz_locked_SPI
- description: 0x81=locked
+ - name: APSCT_PLL_clr_lol
+ rw: rw
+ dtype: boolean
+# monitor: true
driver: I2C_CLK
- devreg: PLL1.PLL_stat
- width: 8
- rw: ro
- dtype: uint8
- debug: True
+ devreg: IO1.GPIO2
+ bitoffset: 4
+ width: 1
+
+# - name: APSCT_PLL_200MHz_locked_SPI
+# description: 0x81=locked
+# driver: I2C_CLK
+# devreg: PLL2.PLL_stat
+# width: 8
+# rw: ro
+# dtype: uint8
+# debug: True
+
+ # - name: APSCT_PLL_160MHz_locked_SPI
+# description: 0x81=locked
+# driver: I2C_CLK
+# devreg: PLL1.PLL_stat
+# width: 8
+# rw: ro
+# dtype: uint8
+# debug: True
# - name: [APSCT_PLL_r3,APSCT_PLL_r5,APSCT_PLL_r6]
# driver: I2C_CLK
@@ -297,6 +342,7 @@ methods:
- APSCT_PCB_version : Update
- APSCT_PCB_number : Update
- APSCT_PWR_on: Update
+ - LMP_ID: Update
- APSCT_PWR_PLL_200MHz_on: Update
- APSCT_PLL_200MHz_locked: Update
- APSCT_PLL_200MHz_error: Update
@@ -304,24 +350,41 @@ methods:
- APSCT_PLL_160MHz_locked: Update
- APSCT_PLL_160MHz_error: Update
- APSCT_PPS_ignore : Update
+ - APSCT_PLL_clr_lol: Update
+ - APSCT_PLL_200MHz_lol: Update
+ - APSCT_PLL_160MHz_lol: Update
+# - name: APSCT_clr_lol
+# driver: I2C_CLK
+# description: Clear lock-off-lock
+# instructions:
+# - APSCTTR_I2C_error : 0
+
- name: APSCT_200MHz_on
driver: I2C_CLK
description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
instructions:
- APSCTTR_I2C_error : 0
+ - IO1.POL1: 0
+ - IO1.POL2: 0
+ - IO2.POL1: 0
+ - IO2.POL2: 0
- IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO1.CONF2: 0x00
- IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- - IO2.CONF2: 0x03 #
+ - IO2.CONF2: 0xFF #
- IO1.GPIO1: 0x42 #0100 0010 high:200MHz PLL enable, CS high
- - IO1.GPIO2: 0xF8 #PWR enable ##Check if not 4??
+# - IO1.GPIO2: 0xF8 #PWR enable ##Check if not 4??
+ - IO1.GPIO2: 0x28 #PWR enable
- IO2.GPIO1: 0x00 #All low
- - IO2.GPIO2: 0x00 #All low (just inputs)
+# - IO2.GPIO2: 0x00 #All low (just inputs)
- WAIT: 200
- APSCT_PLL200_setup: 0
- WAIT: 200 #ms to wait before checking lock
+ - APSCT_PLL_clr_lol: 1
+ - WAIT: 10 #ms
+ - APSCT_PLL_clr_lol: 0
- APSCTTR_Update: 0 #refresh all settings
- name: APSCT_160MHz_on
@@ -329,18 +392,25 @@ methods:
description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
instructions:
- APSCTTR_I2C_error : 0
+ - IO1.POL1: 0
+ - IO1.POL2: 0
+ - IO2.POL1: 0
+ - IO2.POL2: 0
- IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- IO1.CONF2: 0x00
- IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
- - IO2.CONF2: 0x03 #
+ - IO2.CONF2: 0xFF #
- IO1.GPIO1: 0x00
- IO1.GPIO2: 0x08 #PWR enable ##Check if not 4??
- IO2.GPIO1: 0x42 #0100 0010 high:160MHz PLL enable, CS high
- - IO2.GPIO2: 0x00 #All low (just inputs)
+# - IO2.GPIO2: 0x00 #All low (just inputs)
- WAIT: 200
- APSCT_PLL160_setup: 0
- WAIT: 200 #ms to wait before checking lock
+ - APSCT_PLL_clr_lol: 1
+ - WAIT: 10 #ms
+ - APSCT_PLL_clr_lol: 0
- APSCTTR_Update: 0 #refresh all settings
- name: APSCT_off
@@ -358,45 +428,50 @@ methods:
driver: I2C_CLK
debug: true
instructions:
-# - PLL2.0x03: 0x08 #Set power, this is default
- - PLL2.0x04: 0xCF #
- - PLL2.0x05: 0x97 #was 97, set lock time = =x17?
- - PLL2.0x06: 0x10
-
- - PLL2.0x07: 0x04 #Stop R divider
- - PLL2.0x08: 0x01 #Set R divider
- - PLL2.0x07: 0x00 #Start R divider
-
- - PLL2.0x09: 0x10 #Stop N divider
- - PLL2.0x0A: 0x14 #Set N divider=20, 200MHz/20=10MHz = input clock
- - PLL2.0x09: 0x00 #Start N divider
-
- - PLL2.0x0D: 0x01 #Divider output 1=1
- - PLL2.0x0F: 0x01 #Divider output 2=1
- - PLL2.0x11: 0x01 #Divider output 3=1
- - PLL2.0x13: 0x01 #Divider output 4=1
+ - PLL2.0x04: 0x01 #div a
+ - PLL2.0x05: 0x00 #div b, high
+ - PLL2.0x06: 0x14 #dib b, low
+ - PLL2.0x07: 0x00 # No LOR
+ - PLL2.0x08: 0x3B # Charge pump normal + Status bit
+ - PLL2.0x09: 0x30 # Charge pump current
+ - PLL2.0x0A: 0x00 # Fixed Divide 1
+ - PLL2.0x0B: 0x00
+ - PLL2.0x0C: 0x01
+ - PLL2.0x45: 0x00 # CLK2 as feedback clock input
+ - PLL2.0x3d: 0x08 # OUT0 ON LVDS Standard
+ - PLL2.0x3e: 0x0a # OUT1 OFF
+ - PLL2.0x3f: 0x0a # OUT2 OFF
+ - PLL2.0x40: 0x03 # OUT3 OFF
+ - PLL2.0x41: 0x02 # OUT4 ON LVDS Standard
+ - PLL2.0x4b: 0x80 # OUT0 bypass divider
+ - PLL2.0x4d: 0x80 # OUT1 bypass divider
+ - PLL2.0x4f: 0x80 # OUT2 bypass divider
+ - PLL2.0x51: 0x80 # OUT3 bypass divider
+ - PLL2.0x53: 0x80 # OUT4 bypass divider
+ - PLL2.0x5a: 0x0f # Update registers
- name: APSCT_PLL160_setup
driver: I2C_CLK
debug: true
instructions:
-# - PLL1.0x03: 0x08 #Set power, this is default
- - PLL1.0x04: 0xCF #
- - PLL1.0x05: 0x97 #was 97, set lock time = =x17?
- - PLL1.0x06: 0x10
-
- - PLL1.0x07: 0x04 #Stop R divider
- - PLL1.0x08: 0x01 #Set R divider
- - PLL1.0x07: 0x00 #Start R divider
-
- - PLL1.0x09: 0x10 #Stop N divider
- - PLL1.0x0A: 0x10 #Set N divider=16, 160MHz/16=10MHz = input clock
- - PLL1.0x09: 0x00 #Start N divider
-
- - PLL1.0x0D: 0x01 #Divider output 1=1
- - PLL1.0x0F: 0x01 #Divider output 2=1
- - PLL1.0x11: 0x01 #Divider output 3=1
- - PLL1.0x13: 0x01 #Divider output 4=1
-
-
-
+ - PLL1.0x04: 0x01 #div a
+ - PLL1.0x05: 0x00 #div b, high
+ - PLL1.0x06: 0x10 #dib b, low
+ - PLL1.0x07: 0x00 # No LOR
+ - PLL1.0x08: 0x3B # Charge pump normal + Status bit
+ - PLL1.0x09: 0x30 # Charge pump current
+ - PLL1.0x0A: 0x00 # Fixed Divide 1
+ - PLL1.0x0B: 0x00
+ - PLL1.0x0C: 0x01
+ - PLL1.0x45: 0x00 # CLK2 as feedback clock input
+ - PLL1.0x3d: 0x08 # OUT0 ON LVDS Standard
+ - PLL1.0x3e: 0x0a # OUT1 OFF
+ - PLL1.0x3f: 0x0a # OUT2 OFF
+ - PLL1.0x40: 0x03 # OUT3 OFF
+ - PLL1.0x41: 0x02 # OUT4 ON LVDS Standard
+ - PLL1.0x4b: 0x80 # OUT0 bypass divider
+ - PLL1.0x4d: 0x80 # OUT1 bypass divider
+ - PLL1.0x4f: 0x80 # OUT2 bypass divider
+ - PLL1.0x51: 0x80 # OUT3 bypass divider
+ - PLL1.0x53: 0x80 # OUT4 bypass divider
+ - PLL1.0x5a: 0x0f # Update registers
diff --git a/pypcc/config/APSCTTR_L2TS1.yaml b/pypcc/config/APSCTTR_L2TS1.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..512d1caad9b7a5271f29e9f298ff2df848c8bff1
--- /dev/null
+++ b/pypcc/config/APSCTTR_L2TS1.yaml
@@ -0,0 +1,402 @@
+version: "1.0"
+description: "1234"
+
+drivers:
+ - name: I2C
+ type: i2c
+ parameters: [5] #I2C port number
+ - name: I2C_CLK
+ type: i2c_dev #I2C devices
+ parent: I2C
+ status: APSCTTR_I2C_error
+ - name: SPIbb1
+ type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
+ parent: I2C_CLK
+ devreg: [IO1.GPIO1,IO1.GPIO1,IO1.GPIO1,IO1.GPIO1]
+ parameters: [4,7,5,6]
+ - name: SPIbb2
+ type: spibitbang2 #SPI bitbang via GPIO expander: CLK, SDI,SDO,CS
+ parent: I2C_CLK
+ devreg: [IO2.GPIO1,IO2.GPIO1,IO2.GPIO1,IO2.GPIO1]
+ parameters: [4,7,5,6]
+
+#This is the I2C devices in the RCU
+device_registers:
+ - name: IO
+ dim: 2
+ description: IO-Expander (TCA6416APWR)
+ address: [0x20,0x21]
+ driver: I2C_CLK
+ registers:
+ - name: CONF1
+ description: Direction of port1
+ address: 6
+ store: True
+ - name: CONF2
+ description: Direction of port2
+ address: 7
+ store: True
+ - name: GPIO1
+ description: Input/Ouput port 1
+ address: [0,2] #Read / Write address different
+ store: True
+ - name: GPIO2
+ description: Input/Ouput port 2
+ address: [1,3] #Read / Write address different
+ store: True
+
+ - name: PLL2
+ driver: SPIbb1
+ registers:
+ - name: PLL_stat
+ description: PLL locked status
+ address: 0x0
+ - {name: r3, address: 0x03}
+ - {name: r5, address: 0x05}
+ - {name: r6, address: 0x06}
+
+ - name: PLL1
+ driver: SPIbb2
+ registers:
+ - name: PLL_stat
+ description: PLL locked status
+ address: 0x0
+ - {name: r3, address: 0x03}
+ - {name: r5, address: 0x05}
+ - {name: r6, address: 0x06}
+
+ - name: ROM
+ description: 24AA02UIDT
+ address: 0x50
+ driver: I2C_CLK
+ registers:
+ - name: ID
+ description: Random
+ address: 0xfc
+ - name: Version
+ description: Set in production
+ address: 0
+ - name: Serial
+ address: 0x20
+
+ - name: VSENSE
+ description: Monitor ADC
+ address: 0x74
+ device: LTC2495
+ driver: I2C_CLK
+ registers:
+ - name: V_0
+ address: 0xB080
+ wait: 250
+ - name: V_1
+ address: 0xB880
+ wait: 250
+ - name: V_2
+ address: 0xB180
+ wait: 250
+ - name: V_3
+ address: 0xB980
+ wait: 250
+ - name: V_4
+ address: 0xB280
+ wait: 250
+ - name: V_5
+ address: 0xBA80
+ wait: 250
+ - name: V_6
+ address: 0xB380
+ wait: 250
+ - name: Temp
+ address: 0xA0C0
+ wait: 250
+
+
+variables:
+ - name: APSCTTR_I2C_error
+ description: 0=good, >0 indicates an I2C communication error
+ driver: I2C_CLK
+ rw: ro #server RW variable, not linked to IO
+ dtype: uint8
+
+ - name: APSCTTR_monitor_rate
+ description: Monitor rate in seconds
+ rw: variable
+ dtype: uint8
+
+ - name: APSCTTR_translator_busy
+ description: True when I2C line busy
+ rw: ro #server variable, not linked to IO
+ dtype: boolean
+ dim: 1
+
+ - name: APSCT_PCB_ID
+ description: Unique PCB ID
+ driver: I2C_CLK
+ devreg: ROM.ID
+ width: 32
+ rw: ro
+ dtype: uint32
+
+ - name: APSCT_PCB_version
+ description: Version number
+ driver: I2C_CLK
+ devreg: ROM.Version
+ width: 0x80 #16 characters
+ rw: ro
+ dtype: string
+
+ - name: APSCT_PCB_number
+ description: PCB number (astron.nl/webforms/IenS-Boarden/view.php?id=xxx)
+ driver: I2C_CLK
+ devreg: ROM.Serial
+ width: 0x80 #16 characters
+ rw: ro
+ dtype: string
+
+
+ - name: [APSCT_PWR_PLL_200MHz_on,APSCT_PWR_PLL_160MHz_on]
+ description: CLK power status. Controlled by APSCT_xxxMHz_ON and APSCT_OFF
+ rw: ro
+ dtype: boolean
+ driver: I2C_CLK
+ devreg: [IO1.GPIO1,IO2.GPIO1]
+ bitoffset: 1
+ width: 1
+
+ - name: APSCT_PWR_on
+ description: CLK power status. Controlled by APSCT_xxxMHz_ON and APSCT_OFF
+ rw: ro
+ dtype: boolean
+ driver: I2C_CLK
+ devreg: IO1.GPIO2
+ bitoffset: 3
+ width: 1
+
+ - name: APSCT_PPS_ignore
+ rw: rw
+ dtype: boolean
+ driver: I2C_CLK
+ devreg: IO1.GPIO2
+ bitoffset: 2
+ width: 1
+
+ - name: [APSCT_INPUT_10MHz_good,APSCT_INPUT_PPS_good]
+ rw: ro
+ dtype: boolean
+ driver: I2C_CLK
+ devreg: IO2.GPIO2
+ bitoffset: [0,1]
+ width: 1
+ monitor: true
+
+
+ - name: [APSCT_PLL_200MHz_locked,APSCT_PLL_160MHz_locked]
+# description: First status pin give lock status
+ rw: ro
+ dtype: boolean
+ monitor: true
+ driver: I2C_CLK
+ devreg: [IO1.GPIO1,IO2.GPIO1]
+ bitoffset: 2
+ width: 1
+
+ - name: [APSCT_PLL_200MHz_error,APSCT_PLL_160MHz_error]
+# description: Second status pin give error
+ rw: ro
+ dtype: boolean
+ monitor: true
+ driver: I2C_CLK
+ devreg: [IO1.GPIO1,IO2.GPIO1]
+ bitoffset: 3
+ width: 1
+
+ - name: APSCT_PLL_200MHz_locked_SPI
+ description: 0x81=locked
+ driver: I2C_CLK
+ devreg: PLL2.PLL_stat
+ width: 8
+ rw: ro
+ dtype: uint8
+ debug: True
+
+ - name: APSCT_PLL_160MHz_locked_SPI
+ description: 0x81=locked
+ driver: I2C_CLK
+ devreg: PLL1.PLL_stat
+ width: 8
+ rw: ro
+ dtype: uint8
+ debug: True
+
+# - name: [APSCT_PLL_r3,APSCT_PLL_r5,APSCT_PLL_r6]
+# driver: I2C_CLK
+# devreg: [PLL.r3,PLL.r5,PLL.r6]
+# width: 8
+# rw: ro
+# dtype: uint8
+# debug: True
+
+ - name: [APSCT_IO1_GPIO1,APSCT_IO1_GPIO2,APSCT_IO2_GPIO1,APSCT_IO2_GPIO2]
+ driver: I2C_CLK
+ devreg: [IO1.GPIO1,IO1.GPIO2,IO2.GPIO1,IO2.GPIO2]
+ width: 8
+ rw: ro
+ dtype: uint8
+ debug: True
+
+ - name: APSCT_IO2_GPIO1
+ driver: I2C_CLK
+ devreg: IO2.GPIO1
+ width: 8
+ rw: ro
+ dtype: uint8
+ debug: True
+
+ - name: APSCT_TEMP
+ description: Temperature sensor on PCB
+ driver: I2C_CLK
+ devreg: VSENSE.Temp
+ width: 23
+ scale: 3.8265e-3
+ convert_unit: Kelvin2Celsius
+ rw: ro
+ dtype: double
+ monitor: true
+
+ - name: [APSCT_PWR_INPUT_3V3,APSCT_PWR_PLL_160MHz_3V3,APSCT_PWR_PLL_200MHz_3V3,APSCT_PWR_CLKDIST1_3V3,APSCT_PWR_CLKDIST2_3V3,APSCT_PWR_PPSDIST_3V3,APSCT_PWR_CTRL_3V3]
+ driver: I2C_CLK
+ devreg: [VSENSE.V_0,VSENSE.V_1,VSENSE.V_2,VSENSE.V_3,VSENSE.V_4,VSENSE.V_5,VSENSE.V_6]
+ width: 23
+ scale: 1.12165e-6
+ rw: ro
+ dtype: double
+ monitor: true
+
+
+methods:
+ - name: APSCTTR_Init #Called after startup to load. Should have all stored registers
+ driver: I2C_CLK
+ debug: True
+ instructions:
+ - APSCTTR_I2C_error : 0
+ - APSCT_IO1_GPIO1 : Update
+ - APSCT_IO1_GPIO2 : Update
+ - APSCT_IO2_GPIO1 : Update
+ - APSCT_IO2_GPIO2 : Update
+ - IO1.CONF1: Update
+ - IO1.CONF2: Update
+ - IO2.CONF1: Update
+ - IO2.CONF2: Update
+ - APSCTTR_Update: 0
+
+ - name: APSCTTR_Update
+ driver: I2C_CLK
+ debug: True
+ instructions:
+ - APSCT_PCB_ID : Update
+ - APSCT_PCB_version : Update
+ - APSCT_PCB_number : Update
+ - APSCT_PWR_on: Update
+ - APSCT_PWR_PLL_200MHz_on: Update
+ - APSCT_PLL_200MHz_locked: Update
+ - APSCT_PLL_200MHz_error: Update
+ - APSCT_PWR_PLL_160MHz_on: Update
+ - APSCT_PLL_160MHz_locked: Update
+ - APSCT_PLL_160MHz_error: Update
+ - APSCT_PPS_ignore : Update
+
+ - name: APSCT_200MHz_on
+ driver: I2C_CLK
+ description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
+ instructions:
+ - APSCTTR_I2C_error : 0
+ - IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+ - IO1.CONF2: 0x00
+ - IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+ - IO2.CONF2: 0x03 #
+ - IO1.GPIO1: 0x42 #0100 0010 high:200MHz PLL enable, CS high
+ - IO1.GPIO2: 0xF8 #PWR enable ##Check if not 4??
+ - IO2.GPIO1: 0x00 #All low
+ - IO2.GPIO2: 0x00 #All low (just inputs)
+
+ - WAIT: 200
+ - APSCT_PLL200_setup: 0
+ - WAIT: 200 #ms to wait before checking lock
+ - APSCTTR_Update: 0 #refresh all settings
+
+ - name: APSCT_160MHz_on
+ driver: I2C_CLK
+ description: Configure clock. Monitored using APSCT_PWR_on, APSCT_PLL_error and APSCT_PLL_locked
+ instructions:
+ - APSCTTR_I2C_error : 0
+ - IO1.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+ - IO1.CONF2: 0x00
+ - IO2.CONF1: 0x2C #0010 1100 PPS/PWR output, SCLK,CS,SDI
+ - IO2.CONF2: 0x03 #
+ - IO1.GPIO1: 0x00
+ - IO1.GPIO2: 0x08 #PWR enable ##Check if not 4??
+ - IO2.GPIO1: 0x42 #0100 0010 high:160MHz PLL enable, CS high
+ - IO2.GPIO2: 0x00 #All low (just inputs)
+
+ - WAIT: 200
+ - APSCT_PLL160_setup: 0
+ - WAIT: 200 #ms to wait before checking lock
+ - APSCTTR_Update: 0 #refresh all settings
+
+ - name: APSCT_off
+ driver: I2C_CLK
+ description: Switch clock off. Monitored using APSCT_PWR_on
+ instructions:
+ - APSCTTR_I2C_error : 0
+ - IO1.GPIO1: 0x00
+ - IO1.GPIO2: 0x00
+ - IO2.GPIO1: 0x00
+ - IO2.GPIO2: 0x00
+ - APSCTTR_Update: 0 #refresh all settings
+
+ - name: APSCT_PLL200_setup
+ driver: I2C_CLK
+ debug: true
+ instructions:
+# - PLL2.0x03: 0x08 #Set power, this is default
+ - PLL2.0x04: 0xCF #
+ - PLL2.0x05: 0x97 #was 97, set lock time = =x17?
+ - PLL2.0x06: 0x10
+
+ - PLL2.0x07: 0x04 #Stop R divider
+ - PLL2.0x08: 0x01 #Set R divider
+ - PLL2.0x07: 0x00 #Start R divider
+
+ - PLL2.0x09: 0x10 #Stop N divider
+ - PLL2.0x0A: 0x14 #Set N divider=20, 200MHz/20=10MHz = input clock
+ - PLL2.0x09: 0x00 #Start N divider
+
+ - PLL2.0x0D: 0x01 #Divider output 1=1
+ - PLL2.0x0F: 0x01 #Divider output 2=1
+ - PLL2.0x11: 0x01 #Divider output 3=1
+ - PLL2.0x13: 0x01 #Divider output 4=1
+
+ - name: APSCT_PLL160_setup
+ driver: I2C_CLK
+ debug: true
+ instructions:
+# - PLL1.0x03: 0x08 #Set power, this is default
+ - PLL1.0x04: 0xCF #
+ - PLL1.0x05: 0x97 #was 97, set lock time = =x17?
+ - PLL1.0x06: 0x10
+
+ - PLL1.0x07: 0x04 #Stop R divider
+ - PLL1.0x08: 0x01 #Set R divider
+ - PLL1.0x07: 0x00 #Start R divider
+
+ - PLL1.0x09: 0x10 #Stop N divider
+ - PLL1.0x0A: 0x10 #Set N divider=16, 160MHz/16=10MHz = input clock
+ - PLL1.0x09: 0x00 #Start N divider
+
+ - PLL1.0x0D: 0x01 #Divider output 1=1
+ - PLL1.0x0F: 0x01 #Divider output 2=1
+ - PLL1.0x11: 0x01 #Divider output 3=1
+ - PLL1.0x13: 0x01 #Divider output 4=1
+
+
+
diff --git a/pypcc/config/UNB2TR.yaml b/pypcc/config/UNB2TR.yaml
index a804f92b67ee2bd98dc848de9517ba41e2b300f5..08d98afe0d0e0d29713a9e99c9ea999aca0f98cd 100644
--- a/pypcc/config/UNB2TR.yaml
+++ b/pypcc/config/UNB2TR.yaml
@@ -52,6 +52,10 @@ drivers:
type: gpio
parameters: [11,13]
+ - name: I2C_reset_GPIO
+ type: gpio
+ parameters: [15,15]
+
#This is the I2C devices in the RCU
device_registers:
@@ -266,6 +270,15 @@ variables:
dtype: boolean
dim: 2
+ - name: UNB2_I2C_reset
+ driver: I2C_reset_GPIO
+ mask: UNB2_mask
+ width: 1
+ rw: rw
+ dtype: boolean
+ dim: 2
+# convert_unit: bool_invert
+
- name: UNB2_Front_Panel_LED_colour
description: bit 0=Red, 1=Blue, 2=Green
mask: UNB2_mask
@@ -483,7 +496,8 @@ methods:
debug: True
instructions:
- UNB2TR_I2C_error: 0
- - UNB2_I2C_enabled: 1 #Make sure I2C switches are enabled
+ - UNB2_I2C_enabled: 1 #Make sure UNB2 I2C switches are enabled
+ - UNB2_I2C_reset: 1 #Make sure APSCT I2C switches are enabled
- UNB2_PCB_ID: Update
- UNB2_PCB_version: Update
- UNB2_PCB_number: Update
diff --git a/pypcc/config/UNB2TR_L2TS1.yaml b/pypcc/config/UNB2TR_L2TS1.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..a804f92b67ee2bd98dc848de9517ba41e2b300f5
--- /dev/null
+++ b/pypcc/config/UNB2TR_L2TS1.yaml
@@ -0,0 +1,511 @@
+version: "0.0"
+description: "UNB2 DTS first draft"
+
+drivers:
+ - name: I2C1
+ type: i2c_switch2
+ devreg: [APSCT_SWITCH.MASK,UB2_SWITCH1.MASK,UB2_SWITCH2.MASK]
+ parameters: [3,0,0,0] #I2C port number, 3x switch reset pins
+
+ - name: switch_UNB2
+ type: i2c_array
+ parent: I2C1
+ parameters: [0,1] #lookup table
+ I2Ccut: 10
+ status: UNB2TR_I2C_bus_error
+
+ - name: switch_PS
+ type: i2c_array2
+ parent: I2C1
+ parameters: [0,1, 4,4]
+ status: UNB2TR_I2C_bus_PS_error
+
+ - name: switch_FP
+ type: i2c_array2
+ parent: I2C1
+ parameters: [0,1, 5,5]
+ status: UNB2TR_I2C_bus_FP_error
+
+ - name: switch_QSFP
+ type: i2c_array2 #An array of similar devices connected to an I2C switch
+ parent: I2C1
+ parameters: [0,1, 0,3, 0,3, 6,7] #Parameters: APSCT_Switch, main switch, 2nd switch, 2nd switch
+ status: UNB2TR_I2C_bus_QSFP_error
+
+ - name: switch_DDR4
+ type: i2c_array2
+ parent: I2C1
+ parameters: [0,1, 0,3, 4,4]
+ status: UNB2TR_I2C_bus_DDR4_error
+
+ - name: switch_FPGA_PS
+ type: i2c_array2
+ parent: I2C1
+ parameters: [0,1, 0,3, 5,5]
+ status: UNB2TR_I2C_bus_FPGA_PS_error
+
+ - name: GPIO
+ type: gpio
+ parameters: [19,26]
+
+ - name: I2C_GPIO
+ type: gpio
+ parameters: [11,13]
+
+
+#This is the I2C devices in the RCU
+device_registers:
+- name: APSCT_SWITCH #not in LTS
+ description: Uniboard select switch on APSCT
+ address: 0x70
+ device: TCA9548
+ driver: I2C1
+ registers:
+ - name: MASK
+- name: UB2_SWITCH1
+ description: UNB2 primary switch
+ address: 0x71
+ device: TCA9548
+ driver: I2C1
+ registers:
+ - name: MASK
+- name: UB2_SWITCH2
+ description: UNB2 secondary switch
+ address: 0x72
+ device: TCA9548
+ driver: I2C1
+ registers:
+ - name: MASK
+
+- name: FP_IO
+ description: IO-Expander for front panel
+ address: 0x41
+ device: PCA9536
+ driver: switch_FP
+ registers:
+ - name: CONF #default 0xff = all input
+ description: Direction of GPIO
+ address: 3
+ - name: GPIO
+ description: Input/Ouput port
+ address: [0,1] #Read / Write address different
+ store: True
+
+
+- name: DC_DC
+ address: 0x2C
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_CORE
+ address: 0x1
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_ERAM
+ address: 0xD
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_RXGXB
+ address: 0xE
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_TXGXB
+ address: 0xF
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_HGXB
+ address: 0x10
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_PGM
+ address: 0x11
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+- name: POL_QSFP0
+ address: 0x2
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_QSFP1
+ address: 0x1
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_SW1V2
+ address: 0xF
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_SWPHY
+ address: 0xE
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+- name: POL_CLOCK
+ address: 0xD
+ driver: I2C_switch2
+ registers:
+ - { name: "TEMP", address: 0x8D, crc: True}
+ - { name: "VIN" , address: 0x88, crc: True}
+ - { name: "VOUT", address: 0x8B, crc: True}
+ - { name: "IOUT", address: 0x8C, crc: True}
+
+variables:
+
+#When I2C bus timeout, bus_error set to False. Can we set to True again to retry.
+ - name: UNB2TR_I2C_bus_error
+ driver: switch_UNB2
+ rw: ro
+ dtype: uint8
+ dim: 2
+ - name: UNB2TR_I2C_bus_FP_error
+ driver: switch_UNB2
+ rw: hidden
+ dtype: uint8
+ dim: 2
+ - name: UNB2TR_I2C_bus_QSFP_error
+ driver: switch_QSFP
+ rw: ro
+ dtype: uint8
+ dim: 48
+ dim2: [24,2]
+ - name: UNB2TR_I2C_bus_DDR4_error
+ driver: switch_QSFP
+ rw: ro
+ dtype: uint8
+ dim: 8
+ dim2: [4,2]
+ - name: UNB2TR_I2C_bus_FPGA_PS_error
+ driver: switch_FPGA_PS
+ rw: ro
+ dtype: uint8
+ dim: 8
+ dim2: [4,2]
+ - name: UNB2TR_I2C_bus_PS_error
+ driver: switch_PS
+ rw: ro
+ dtype: uint8
+ dim: 2
+
+ - name: UNB2TR_monitor_rate
+ description: Monitor rate in seconds
+ rw: variable
+ dtype: uint8
+
+ - name: UNB2TR_translator_busy
+ description: False when idle
+ rw: ro #server variable, not linked to IO
+ dtype: boolean
+
+##Central MP for whole Uniboard2
+ - name: UNB2_mask
+ rw: variable #translator variable
+ dtype: boolean
+ dim: 2
+
+ - name: UNB2_PWR_on
+ driver: GPIO
+ mask: UNB2_mask
+ width: 1
+ rw: ro
+ dtype: boolean
+ convert_unit: bool_invert
+ dim: 2
+
+ - name: UNB2_I2C_enabled
+ driver: I2C_GPIO
+ mask: UNB2_mask
+ width: 1
+ rw: ro
+ dtype: boolean
+ dim: 2
+
+ - name: UNB2_Front_Panel_LED_colour
+ description: bit 0=Red, 1=Blue, 2=Green
+ mask: UNB2_mask
+ driver: switch_FP
+ devreg: FP_IO.GPIO
+# bitoffset: 4
+ width: 3
+ rw: rw
+ dtype: uint8
+ dim: 2
+
+ - name: UNB2_PCB_version
+ driver: switch_UNB2
+ devreg: 0x50.0
+ width: 0x80 #16 char
+ rw: ro
+ dtype: string
+ dim: 2
+
+ - name: UNB2_PCB_number
+ description: PCB number (astron.nl/webforms/IenS-Boarden/view.php?id=xxx)
+ driver: switch_UNB2
+ devreg: 0x50.0x20
+ width: 0x80 #16 characters
+ rw: ro
+ dtype: string
+ dim: 2
+
+ - name: UNB2_PCB_ID
+ driver: switch_UNB2
+ devreg: 0x50.0xFC
+ width: 32
+ rw: ro
+ dtype: uint32
+ dim: 2
+
+
+ - name: [UNB2_DC_DC_48V_12V_VIN,UNB2_DC_DC_48V_12V_VOUT]
+ driver: switch_PS
+ devreg: [DC_DC.VIN,DC_DC.VOUT]
+ width: 16
+ rw: ro
+ dtype: double
+ endian: "<"
+ scale: 4.8828125e-4 #2^-11
+ dim: 2
+ monitor: true
+
+ - name: [UNB2_DC_DC_48V_12V_VOUT_MODE,UNB2_POL_QSFP_N01_VOUT_MODE,UNB2_POL_QSFP_N23_VOUT_MODE,UNB2_POL_SWITCH_1V2_VOUT_MODE,UNB2_POL_SWITCH_PHY_VOUT_MODE,UNB2_POL_CLOCK_VOUT_MODE]
+ driver: switch_PS
+ devreg: [0x2C.0x20,0x2.0x20,0x1.0x20,0xF.0x20,0xE.0x20,0xD.0x20]
+ width: 8
+ rw: ro
+ dtype: uint8
+ dim: 2
+ debug: true
+ monitor: true
+
+ - name: [UNB2_POL_QSFP_N01_VOUT,UNB2_POL_QSFP_N23_VOUT]
+ driver: switch_PS
+# devreg: [0x2.0x8B,0x1.0x8B]
+ devreg: [POL_QSFP0.VOUT,POL_QSFP1.VOUT]
+ width: 16
+ rw: ro
+ dtype: double
+ endian: "<"
+ scale: 1.220703125e-4 #2^-13
+ dim: 2
+ monitor: true
+
+ - name: [UNB2_POL_SWITCH_1V2_VOUT,UNB2_POL_SWITCH_PHY_VOUT,UNB2_POL_CLOCK_VOUT]
+ driver: switch_PS
+# devreg: [0xF.0x8B,0xE.0x8B,0xD.0x8B]
+ devreg: [POL_SW1V2.VOUT,POL_SWPHY.VOUT,POL_CLOCK.VOUT]
+ width: 16
+ rw: ro
+ dtype: double
+ endian: "<"
+ scale: 2.44140625e-4 #2^-12
+ dim: 2
+ monitor: true
+
+ - name: [UNB2_DC_DC_48V_12V_IOUT,UNB2_POL_QSFP_N01_IOUT,UNB2_POL_QSFP_N23_IOUT,UNB2_POL_SWITCH_1V2_IOUT,UNB2_POL_SWITCH_PHY_IOUT,UNB2_POL_CLOCK_IOUT]
+ driver: switch_PS
+# devreg: [DC_DC.IOUT,0x2.0x8C,0x1.0x8C,0xF.0x8C,0xE.0x8C,0xD.0x8C]
+ devreg: [DC_DC.IOUT,POL_QSFP0.IOUT,POL_QSFP1.IOUT,POL_SW1V2.IOUT,POL_SWPHY.IOUT,POL_CLOCK.IOUT]
+ width: 16
+ rw: ro
+ dtype: double
+ scale: smbus_2bytes_to_float
+ dim: 2
+ monitor: true
+
+ - name: [UNB2_DC_DC_48V_12V_TEMP,UNB2_POL_QSFP_N01_TEMP,UNB2_POL_QSFP_N23_TEMP,UNB2_POL_SWITCH_1V2_TEMP,UNB2_POL_SWITCH_PHY_TEMP,UNB2_POL_CLOCK_TEMP]
+ driver: switch_PS
+# devreg: [DC_DC.TEMP,0x2.0x8D,0x1.0x8D,0xF.0x8D,0xE.0x8D,0xD.0x8D]
+ devreg: [DC_DC.TEMP,POL_QSFP0.TEMP,POL_QSFP1.TEMP,POL_SW1V2.TEMP,POL_SWPHY.TEMP,POL_CLOCK.TEMP]
+ width: 16
+ rw: ro
+ dtype: double
+ scale: smbus_2bytes_to_float
+ dim: 2
+ monitor: true
+
+##Local MP per FPGA node
+ - name: UNB2_FPGA_DDR4_SLOT_TEMP
+ driver: switch_DDR4
+ devreg: [0x18.0x5,0x19.0x5]
+ width: 13
+ rw: ro
+ dtype: double
+ scale: 0.0625
+ dim: 16
+ dim2: [8,2]
+ monitor: true
+
+ - name: UNB2_FPGA_DDR4_SLOT_PART_NUMBER
+ driver: switch_DDR4
+ devreg: [0x18.0x149,0x19.0x149]
+ width: 160
+ rw: hidden #ro
+ dtype: string
+ dim: 16
+ dim2: [8,2]
+# monitor: true
+
+ - name: [UNB2_FPGA_POL_CORE_IOUT,UNB2_FPGA_POL_ERAM_IOUT,UNB2_FPGA_POL_RXGXB_IOUT,UNB2_FPGA_POL_TXGXB_IOUT,UNB2_FPGA_POL_HGXB_IOUT,UNB2_FPGA_POL_PGM_IOUT]
+ driver: switch_FPGA_PS
+# devreg: [0x1.0x8C,0xD.0x8C,0xE.0x8C,0xF.0x8C,0x10.0x8C,0x11.0x8C]
+ devreg: [POL_CORE.IOUT,POL_ERAM.IOUT,POL_RXGXB.IOUT,POL_TXGXB.IOUT,POL_HGXB.IOUT,POL_PGM.IOUT]
+ width: 16
+ rw: ro
+ dtype: double
+ scale: smbus_2bytes_to_float
+ dim: 8
+ dim2: [4,2]
+ monitor: true
+
+ - name: [UNB2_FPGA_POL_CORE_TEMP,UNB2_FPGA_POL_ERAM_TEMP,UNB2_FPGA_POL_RXGXB_TEMP,UNB2_FPGA_POL_TXGXB_TEMP,UNB2_FPGA_POL_HGXB_TEMP,UNB2_FPGA_POL_PGM_TEMP]
+ driver: switch_FPGA_PS
+# devreg: [0x1.0x8D,0xD.0x8D,0xE.0x8D,0xF.0x8D,0x10.0x8D,0x11.0x8D]
+ devreg: [POL_CORE.TEMP,POL_ERAM.TEMP,POL_RXGXB.TEMP,POL_TXGXB.TEMP,POL_HGXB.TEMP,POL_PGM.TEMP]
+ width: 16
+ rw: ro
+ dtype: double
+ scale: smbus_2bytes_to_float
+ dim: 8
+ dim2: [4,2]
+ monitor: true
+
+ - name: [UNB2_FPGA_POL_CORE_VOUT]
+ driver: switch_FPGA_PS
+ devreg: [POL_CORE.VOUT]
+ width: 16
+ rw: ro
+ dtype: double
+ endian: "<"
+ scale: 1.220703125e-4 #2^-13
+ dim: 8
+ dim2: [4,2]
+ monitor: true
+
+ - name: [UNB2_FPGA_POL_ERAM_VOUT,UNB2_FPGA_POL_RXGXB_VOUT,UNB2_FPGA_POL_TXGXB_VOUT,UNB2_FPGA_POL_HGXB_VOUT,UNB2_FPGA_POL_PGM_VOUT]
+ driver: switch_FPGA_PS
+ devreg: [POL_ERAM.VOUT,POL_RXGXB.VOUT,POL_TXGXB.VOUT,POL_HGXB.VOUT,POL_PGM.VOUT]
+# devreg: [0xD.0x8B,0xE.0x8B,0xF.0x8B,0x10.0x8B,0x11.0x8B]
+ width: 16
+ rw: ro
+ dtype: double
+ endian: "<"
+ scale: 2.44140625e-4 #2^-12
+ dim: 8
+ dim2: [4,2]
+ monitor: true
+
+ - name: [UNB2_FPGA_POL_CORE_VOUT_MODE,UNB2_FPGA_POL_ERAM_VOUT_MODE,UNB2_FPGA_POL_RXGXB_VOUT_MODE,UNB2_FPGA_POL_TXGXB_VOUT_MODE,UNB2_FPGA_POL_HGXB_VOUT_MODE,UNB2_FPGA_POL_PGM_VOUT_MODE]
+ driver: switch_FPGA_PS
+ devreg: [0x1.0x20,0xD.0x20,0xE.0x20,0xF.0x20,0x10.0x20,0x11.0x20]
+ width: 8
+ rw: ro
+ dtype: uint8
+ dim: 8
+ dim2: [4,2]
+ debug: true
+# monitor: true
+
+
+##Local MP per FPGA node, QSFP cage
+ - name: UNB2_FPGA_QSFP_CAGE_TEMP
+ driver: switch_QSFP
+ devreg: 0x50.0x16
+ width: 16
+ rw: ro
+ dtype: double
+ scale: 3.90625e-3 #1/256
+ convert_unit: temp_check
+ dim: 48
+ dim2: [24,2]
+ monitor: true
+
+ - name: UNB2_FPGA_QSFP_CAGE_LOS
+ description: Bits for 4 TX, 4 RX channels
+ driver: switch_QSFP
+ devreg: 0x50.0x03
+ width: 8
+ rw: ro
+ dtype: uint8
+ dim: 48
+ dim2: [24,2]
+ monitor: true
+
+methods:
+ - name: UNB2TR_Init #Called after startup to load.
+ driver: switch_UNB2
+ debug: True
+ instructions:
+ - UNB2TR_I2C_error: 0
+ - UNB2_I2C_enabled: 1 #Make sure I2C switches are enabled
+ - UNB2_PCB_ID: Update
+ - UNB2_PCB_version: Update
+ - UNB2_PCB_number: Update
+# - FP_IO.CONF: 0xf8 #bit 0-2 output for LED
+ - UNB2_Front_Panel_LED_colour: Update
+ - UNB2_PWR_on: Update
+
+ - name: UNB2_on
+ mask: UNB2_mask
+ driver: switch_FP
+ instructions:
+ - UNB2_I2C_enabled: 1 #Make sure I2C switches are enabled
+ - FP_IO.CONF: 0xf8 #bit 0-2 output for LED
+ - UNB2_PWR_on: 0 #already inverted
+ - UNB2_Front_Panel_LED_colour: 3 #green
+ - UNB2_PCB_ID: Update
+ - UNB2_PCB_version: Update
+ - WAIT: 5000
+
+ - name: UNB2_off
+ mask: UNB2_mask
+ instructions:
+ - UNB2_PWR_on: 1 #inverted
+ - WAIT: 5000
+# - UNB2_Front_Panel_LED_colour: 2
diff --git a/pypcc/i2cserv/gpio.py b/pypcc/i2cserv/gpio.py
index 74950d2bce32ec58a57b5c57ad1dfcb6583609b5..fbe08e588a435c625a9056919fe3e6b40982417f 100644
--- a/pypcc/i2cserv/gpio.py
+++ b/pypcc/i2cserv/gpio.py
@@ -11,24 +11,24 @@ class gpio(hwdev):
self.pins=config['parameters']
self.Npins=len(self.pins);
GPIO.setmode(GPIO.BCM)
- self.state=[0 for pin in self.pins]
- logging.info(str(("gpio, Pins=",self.state)));
+# self.state=[0 for pin in self.pins]
+# logging.info(str(("gpio, Pins=",self.state)));
for i,pin in enumerate(self.pins):
GPIO.setup(pin,GPIO.OUT)
# for i,pin in enumerate(self.pins):
# GPIO.setup(pin,GPIO.IN)
-# self.state=[GPIO.input(pin) for pin in self.pins]
-# logging.info(str(("gpio, Pins=",self.state)));
+ self.state=[GPIO.input(pin) for pin in self.pins]
+ logging.info(str((config['name']," gpio, Pins=",self.state)));
def OPCUASetVariable(self,varid,var1,data,mask):
logging.info("Set gpio");
if len(mask)!=self.Npins:
- logging.warning("Wrong mask length");
+ if len(mask)>0: logging.warning("GPIO Wrong mask length %i,%i"%(len(mask),self.Npins));
mask=[True]*self.Npins;
if len(data)!=self.Npins:
if len(data)==1: data=[data[0]]*self.Npins;
else:
- logging.warning("Wrong data length");
+ logging.warning("GPIO Wrong data length");
return []
for i,pin in enumerate(self.pins):
if mask[i]:
diff --git a/pypcc/i2cserv/gpio_id.py b/pypcc/i2cserv/gpio_id.py
new file mode 100644
index 0000000000000000000000000000000000000000..4fc24598545cbaf5241a1d768c648b23c9de2677
--- /dev/null
+++ b/pypcc/i2cserv/gpio_id.py
@@ -0,0 +1,34 @@
+#import numpy as np
+from .hwdev import hwdev;
+import logging
+import RPi.GPIO as GPIO
+from pypcc.queuetypes import *
+
+
+class gpio_id(hwdev):
+ def __init__(self,config):
+ hwdev.__init__(self,config);
+ self.pins=config['parameters']
+ self.Npins=len(self.pins);
+ GPIO.setmode(GPIO.BCM)
+ for i,pin in enumerate(self.pins):
+ GPIO.setup(pin,GPIO.IN)
+ logging.info(str((config['name']," gpio, value=",self.get_value())));
+
+ def get_value(self):
+ value=0;
+ for pin in self.pins:
+ value=2*value+1 if GPIO.input(pin) else 2*value
+ return value
+
+ def OPCUASetVariable(self,varid,var1,data,mask):
+ return []
+
+ def OPCUAReadVariable(self,varid,var1,mask):
+ value=self.get_value()
+ logging.info(" gpio, value=%i"%value);
+ Data=OPCUAset(varid,InstType.varSet,[value],mask.copy())
+ return [Data]
+
+
+
diff --git a/pypcc/i2cserv/spibitbang3.py b/pypcc/i2cserv/spibitbang3.py
new file mode 100644
index 0000000000000000000000000000000000000000..f6bbbdad7767e019334a17617c7d923ed0610a02
--- /dev/null
+++ b/pypcc/i2cserv/spibitbang3.py
@@ -0,0 +1,97 @@
+from enum import Enum
+import logging
+import numpy as np
+from .hwdev import hwdev
+
+class SPIBB_pins(Enum):
+ CLK = 0
+ SDI = 1
+ SDO = 2
+ CS = 3
+
+
+class spibitbang3(hwdev):
+ def __init__(self,config):
+ hwdev.__init__(self,config)
+
+ def i2csetget(self,addr,data,reg=None,read=0):
+ if read==0: return self.SetSPIbb(reg,data)
+ elif read==1: return self.GetSPIbb(reg,data)
+ else: logging.warn("Not implemented!")
+ return False;
+
+ def SetSPIbb(self,address,value):
+ CSdev=self.conf['devreg'][SPIBB_pins.CS.value]
+ CSpin=self.conf['parameters'][SPIBB_pins.CS.value]
+ SDIdev=self.conf['devreg'][SPIBB_pins.SDI.value]
+ SDIpin=self.conf['parameters'][SPIBB_pins.SDI.value]
+ CLKdev=self.conf['devreg'][SPIBB_pins.CLK.value]
+ CLKpin=self.conf['parameters'][SPIBB_pins.CLK.value]
+
+ logging.info(str(("SPIbb3 set",address,value)))
+ SetI2C=self.conf['parentcls'].SetVarValue
+ ADC_bytes = 0x00
+ ADC_rw = 0x00 # 0 for write, 1 for read
+ data2 = ( ADC_rw << 23 ) + ( ADC_bytes << 21 ) + ( address << 8 ) + value[0]
+ bit_array = "{0:{fill}24b}".format(data2, fill='0')
+
+ # print(bit_array)
+# SetI2C(CSdev,1,CSpin,[1]) #disable
+ if not(SetI2C(CSdev,1,CSpin,[0])): return False #enable
+ for bit in bit_array:
+ SetI2C(SDIdev,1,SDIpin,[int(bit)])
+ SetI2C(CLKdev,1,CLKpin,[1])
+ SetI2C(CLKdev,1,CLKpin,[0])
+ SetI2C(CSdev,1,CSpin,[1]) #disable
+# SetI2C(SDOdev,1,SDOpin,[1]) #high when finished
+ return True;
+
+ def GetSPIbb(self,reg_address,value):
+ CSdev=self.conf['devreg'][SPIBB_pins.CS.value]
+ CSpin=self.conf['parameters'][SPIBB_pins.CS.value]
+ SDOdev=self.conf['devreg'][SPIBB_pins.SDO.value]
+ SDOpin=self.conf['parameters'][SPIBB_pins.SDO.value]
+ SDIdev=self.conf['devreg'][SPIBB_pins.SDI.value]
+ SDIpin=self.conf['parameters'][SPIBB_pins.SDI.value]
+ CLKdev=self.conf['devreg'][SPIBB_pins.CLK.value]
+ CLKpin=self.conf['parameters'][SPIBB_pins.CLK.value]
+
+
+ logging.info(str(("SPIbb2 get",reg_address)))
+ SetI2C=self.conf['parentcls'].SetVarValue
+ GetI2C=self.conf['parentcls'].GetVarValue
+
+ ADC_bytes = 0x00
+ # ADC_rw = 0x01 # 0 for write, 1 for read
+ #data = (reg_address << 1) + 1 #was 7??
+ ADC_rw = 0x01 # 0 for write, 1 for read
+
+ data = ( ADC_rw << 15) + ( ADC_bytes << 13 ) + reg_address
+
+ SetI2C(CSdev,1,CSpin,[1]) #disable
+ SetI2C(CSdev,1,CSpin,[0]) #enable
+
+ bit_array = "{0:{fill}16b}".format(data, fill='0')
+ for bit in bit_array:
+ SetI2C(SDIdev,1,SDIpin,[int(bit)])
+ SetI2C(CLKdev,1,CLKpin,[0])
+ SetI2C(CLKdev,1,CLKpin,[1])
+
+ # print("read byte")
+ a=[0]
+ N=1 #len(value)
+ ret_value=[0]
+ for i in range(N): value[i]=0
+ for cnt in range(8*(ADC_bytes+1)):
+ SetI2C(CLKdev,1,CLKpin,[0])
+ SetI2C(CLKdev,1,CLKpin,[1]) #read after rising
+ GetI2C(SDOdev,1,SDOpin,ret_value)
+# for i in range(N): value[i]=(value[i]<<1)+ ret_value[i]
+ for i in range(N):
+ if ret_value is None: value[i]=None
+ elif not value[i] is None: value[i]=(value[i]<<1)+ ret_value[i]
+ SetI2C(CLKdev,1,CLKpin,[0])
+ SetI2C(CSdev,1,CSpin,[1]) #disable
+ return True;
+
+
diff --git a/pypcc/pypcc.py b/pypcc/pypcc.py
index 9d5cb779faa8255bfa55d6854f55ce70e3390879..1e121cad119363e3d9e633512116fd602fdb0f28 100755
--- a/pypcc/pypcc.py
+++ b/pypcc/pypcc.py
@@ -1,14 +1,10 @@
-import logging
+from importlib import metadata
import argparse
-from pypcc.opcuaserv import opcuaserv
-from pypcc.opcuaserv import i2client
-from pypcc.opcuaserv import yamlreader
-#from opcuaserv import pypcc2
-from pypcc.i2cserv import i2cthread
+import logging
+import signal
+import sys
import threading
import time
-import sys
-import signal
parser = argparse.ArgumentParser()
parser.add_argument("-s", "--simulator", help="Do not connect to I2c, but simulate behaviour.", action="store_true")
@@ -30,6 +26,14 @@ args = parser.parse_args()
#}
#configure_logger(logstash_host=args.loghost,level=args.loglevel, log_extra=log_extra)
logging.getLogger().setLevel(args.loglevel)
+git_hash=metadata.metadata("pypcc")["Summary"]
+logging.info("Git Hash="+git_hash)
+
+from pypcc.opcuaserv import opcuaserv
+from pypcc.opcuaserv import i2client
+from pypcc.opcuaserv import yamlreader
+#from opcuaserv import pypcc2
+from pypcc.i2cserv import i2cthread
RunTimer=True;
def signal_handler(sig, frame):
@@ -64,6 +68,7 @@ configs=[]
if not(args.test):
handler=opcuaserv.InitServer(port=args.port)
logging.info("Load OPCUA variables & start i2c listing thread")
+ opcuaserv.AddVarR("pypcc_git_hash",git_hash,[],False)
for i,name in enumerate(I2Cports):
RCU_I2C=I2Cclients[i]
RCU_conf=yamlreader.yamlreader(RCU_I2C,yamlfile=name)
diff --git a/requirements.txt b/requirements.txt
index d2f21bb2cfefb28570eed8dce8456e0dd0466ff1..eaed495371b1da5bb986fc60982cb8c990c9c6e5 100644
--- a/requirements.txt
+++ b/requirements.txt
@@ -1,4 +1,4 @@
-git+https://github.com/amaork/libi2c.git; platform_system == "linux"
+git+https://github.com/amaork/libi2c.git; platform_system == "Linux"
asyncua
numpy
recordclass
diff --git a/scripts/apsct_test.py b/scripts/apsct_test.py
new file mode 100644
index 0000000000000000000000000000000000000000..0d0c20823a8afbbb4bf8d04213b4d3bc9e760ae0
--- /dev/null
+++ b/scripts/apsct_test.py
@@ -0,0 +1,41 @@
+from test_common import *
+from time import sleep
+connect("opc.tcp://localhost:4843/")
+
+if True:
+ print("Switch off")
+ callmethod("APSCT_off")
+ sleep(0.5)
+ wait_not_busy("APSCTTR_translator_busy_R",timeout_sec=3)
+
+if True:
+ print("Setup 160MHz")
+ callmethod("APSCT_160MHz_on")
+ sleep(0.5)
+ wait_not_busy("APSCTTR_translator_busy_R",timeout_sec=3)
+
+if False:
+ print("Setup 200MHz")
+ callmethod("APSCT_200MHz_on")
+ sleep(0.5)
+ wait_not_busy("APSCTTR_translator_busy_R",timeout_sec=3)
+
+if True:
+ print("Clear lol")
+ set_value("APSCT_PLL_clr_lol_RW",True)
+ sleep(0.1)
+ set_value("APSCT_PLL_clr_lol_RW",False)
+
+if False:
+ print("Get monitor values")
+ set_value("APSCTTR_monitor_rate_RW",1)
+ sleep(3)
+ set_value("APSCTTR_monitor_rate_RW",30)
+
+
+names=get_all_variables()
+for name in names:
+ att=get_value(name)
+ print(name,[att])
+
+disconnect();
diff --git a/scripts/git_hash.py b/scripts/git_hash.py
new file mode 100644
index 0000000000000000000000000000000000000000..6a44e1cc3368d06228c41e041dd8ed02c40ab555
--- /dev/null
+++ b/scripts/git_hash.py
@@ -0,0 +1,4 @@
+from test_common import *
+connect("opc.tcp://localhost:4840/")
+print(get_value("pypcc_git_hash"))
+disconnect();
diff --git a/scripts/test_common.py b/scripts/test_common.py
index 634fc8067bf6e679095e3d21ada8abe8421d4f97..02a36ba0596ef0217997ec45b3081c41504aeab0 100644
--- a/scripts/test_common.py
+++ b/scripts/test_common.py
@@ -41,6 +41,16 @@ def set_value(name,value,tp=None):
else:
var1.set_value(value,tp)
+def get_all_variables():
+ vars0=[]
+ obj0=root.get_child(["0:Objects"])
+ for nodeid in obj0.get_children():
+ ch = client.get_node(nodeid)
+ name=ch.get_display_name().Text
+ if ch.get_node_class()==ua.NodeClass.Variable:
+ vars0.append(name)
+ return vars0
+
def get_debug_value(name):
var1 = root.get_child(["0:Objects", "2:DEBUG", "2:"+name])
diff --git a/setup.py b/setup.py
index 25adcbf6c8ede44d4565fb729756ec288db654f7..16a86eba70e3e6396395cf7287db5637d6549b8c 100644
--- a/setup.py
+++ b/setup.py
@@ -1,9 +1,26 @@
import setuptools
+import subprocess
+def _get_version_hash():
+ """Talk to git and find out the tag/hash of our latest commit"""
+ try:
+ p = subprocess.Popen(["git", "rev-parse","HEAD"],
+# p = subprocess.Popen(["git", "log","-1","--format='%H'"],
+ stdout=subprocess.PIPE)
+ except EnvironmentError:
+ print("Couldn't run git to get a version number for setup.py")
+ return
+ ver = p.communicate()[0]
+ ver=ver.strip()
+ ver=str(ver)[2:-1]
+ print("Git hash=",ver)
+ return ver
+
#with open('requirements.txt') as f:
# required = f.read().splitlines()
# Requires: setup.cfg
-setuptools.setup(install_requires=["asyncua",
+setuptools.setup(description=_get_version_hash(),
+ install_requires=["asyncua",
"numpy",
"recordclass",
"pyyaml",