TEC screens requiring large aterm kernels
We are finding that the typical aterm kernel size is unable to cater for a reasonably complex and detailed TEC screen. This ticket is to track both:
- Changes required to IDG to better cater for such TEC screens
- Recommendations for building better suited TEC screens.
When the kernel size is too small, this results in severe deformation of the dirty image. In particular:
- The edges of the TEC screen, whose size is frequency dependent, becomes apparent as a a grid at the edge of the dirty image. During cleaning, this grid is picked up as real sources and causes the cleaning process to diverge
- Large scale 'smudging' occurs across the dirty image, at those locations where there are edges in the TEC screen, for example, between facets
- Even at high kernel sizes, TEC screen edges result in extra flux being deposited into the dirty image, on the order of 1500 mJy.
wsclean has a default setting for -aterm-kernel-size=5. For the faceted TEC screen I am providing as an example here, this value needs to be set to +400 - the precise value is not clear as IDG throws a memory error for kernel sizes greater than ~500.
To reproduce this issue, I provide a full (calibrated) MWA measurement set and TEC screen (5Gb): https://drive.google.com/open?id=1rRnHwoworBeBV9zoU7hKJ2HHOpHnd1Ka
The wsclean command I issue is:
wsclean -name forBas -mwa-path . -size 2000 2000 -scale 18asec -use-idg -idg-mode hybrid -aterm-config aterm.params -aterm-kernel-size 450 -channels-out 6 -join-channels -data-column DATA -deconvolution-channels 1 -fit-spectral-pol 1 -niter 999999 -mgain 0.8 -auto-mask 3 -auto-threshold 1 -no-update-model-required -save-aterms 1217016024-forBas.ms
Some ideas on how to resolve this going forward:
- Verify that the TEC screens are being correctly processed by wsclean and IDG
- Produce diagnostic output for wsclean users to view the TEC screen being applied after kernel size is accounted for (ie. the TEC screen after being fourier transformed there and back again). It needs to be made obvious whether the TEC screen is being sufficiently supported by the kernel.
- Allow for larger kernel sizes in IDG than ~500
- Understand recommendations for constructing TEC screens
- ie. recommend convolving down TEC screens (gaussian? some other kernel?) to reduce fine detail and edges
Large scale grid structure near the edge:
Additional flux deposited throughout image (this is a difference image of the dirty image between kernels sizes of 64 versus 128):